公开(公告)号：US09007111B2

公开(公告)日：2015-04-14

申请号：US14154458

申请日：2014-01-14

Applicant: Texas Instruments Incorporated

Inventor： Steven Bartling ,  Sudhanshu Khanna

IPC: H03K3/356 ,  H03K3/3562

CPC classification number: H03K3/35625 ,  H03K3/3562

Abstract: In an embodiment of the invention, a flip-flop circuit contains a 2-input multiplexer, a master latch, a transfer gate and a slave latch. The scan enable control signals SE and SEN of the multiplexer determine whether data or scan data is input to the master latch. Clock signals CKT and CLKZ and retention control signals RET and RETN determine when the master latch is latched. The slave latch is configured to receive the output of the master latch, a second data bit D2, the clock signals CKT and CLKN, the retain control signals RET and RETN, the slave control signals SS and SSN. The signals CKT, CLKZ, RET, RETN, SS, SS, RE and REN determine whether the output of the master latch or the second data bit D2 is latched in the slave latch. Control signals RET and RETN determine when data is stored in the slave latch during retention mode.

Abstract translation: 在本发明的实施例中，触发器电路包含2输入多路复用器，主锁存器，传输门和从锁存器。 复用器的扫描使能控制信号SE和SEN确定数据还是扫描数据被输入到主锁存器。 时钟信号CKT和CLKZ以及保持控制信号RET和RETN确定主锁存器何时被锁存。 从锁存器被配置为接收主锁存器的输出，第二数据位D2，时钟信号CKT和CLKN，保持控制信号RET和RETN，从控制信号SS和SSN。 信号CKT，CLKZ，RET，RETN，SS，SS，RE和REN确定主锁存器或第二数据位D2的输出是否锁存在从锁存器中。 在保持模式期间，控制信号RET和RETN确定数据是否存储在从锁存器中。

公开(公告)号：US20150054556A1

公开(公告)日：2015-02-26

申请号：US14311831

申请日：2014-06-23

Applicant: Texas Instruments Incorporated

Inventor： Steven Craig Bartling ,  Sudhanshu Khanna

IPC: H03K3/037

CPC classification number: H03K3/0375 ,  H03K3/356008

Abstract: In an embodiment of the invention, a dual-port negative level sensitive reset data retention latch contains a clocked inverter and a dual-port latch. Data is clocked through the clocked inverter when clock signal CKT goes low, CLKZ goes high, reset control signal REN is high and retention control signal RET is low. The dual-port latch is configured to receive the output of the clocked inverter, a second data bit D2, the clock signals CKT and CLKZ, the retain control signal RET, the reset control signal REN and the control signals SS and SSN. The signals CKT, CLKZ, RET, REN, SS and SSN determine whether the output of the clocked inverter or the second data bit D2 is latched in the dual-port latch. Control signal RET determines when data is stored in the dual-port latch during retention mode.

Abstract translation: 在本发明的一个实施例中，双端口负电平敏感复位数据保持锁存器包括时钟反相器和双端口锁存器。 当时钟信号CKT变低，CLKZ变为高电平，复位控制信号REN为高电平，保持控制信号RET为低电平时，数据由时钟反相器提供时钟。 双端口锁存器被配置为接收时钟反相器的输出，第二数据位D2，时钟信号CKT和CLKZ，保持控制信号RET，复位控制信号REN和控制信号SS和SSN。 信号CKT，CLKZ，RET，REN，SS和SSN确定时钟反相器或第二数据位D2的输出是否锁存在双端口锁存器中。 在保持模式期间，控制信号RET确定数据何时存储在双端口锁存器中。

公开(公告)号：US08836398B2

公开(公告)日：2014-09-16

申请号：US13759240

申请日：2013-02-05

Applicant: Texas Instruments Incorporated

Inventor： Steven Bartling ,  Sudhanshu Khanna

IPC: H03K3/289 ,  H03K3/012

CPC classification number: H03K3/012 ,  H03K3/289 ,  H03K3/35625

Abstract: In an embodiment of the invention, a flip-flop circuit contains a 2-input multiplexer, a master latch, a transfer gate and a slave latch. The scan enable control signals SE and SEN of the multiplexer determine whether data or scan data is input to the master latch. The clock signals CLK and CLKN and retention control signals RET and RETN determine when the master latch is latched. The slave latch is configured to receive the output of the master latch, a second data bit D2, the clock signals CLK and CLN, the retain control signals RET and RETN, the slave control signals SS and SSN. The signals CLK, CLKN, RET, RETN, SS and SSN determine whether the output of the master latch or the second data bit D2 is latched in the slave latch. Control signals RET and RETN determine when data is stored in the slave latch during retention mode.

Abstract translation: 在本发明的实施例中，触发器电路包含2输入多路复用器，主锁存器，传输门和从锁存器。 复用器的扫描使能控制信号SE和SEN确定数据还是扫描数据被输入到主锁存器。 时钟信号CLK和CLKN以及保持控制信号RET和RETN确定主锁存器何时被锁存。 从锁存器被配置为接收主锁存器的输出，第二数据位D2，时钟信号CLK和CLN，保持控制信号RET和RETN，从控制信号SS和SSN。 信号CLK，CLKN，RET，RETN，SS和SSN确定主锁存器或第二数据位D2的输出是否锁存在从锁存器中。 在保持模式期间，控制信号RET和RETN确定数据是否存储在从锁存器中。

公开(公告)号：US20140232443A1

公开(公告)日：2014-08-21

申请号：US14154550

申请日：2014-01-14

Applicant: Texas Instruments Incorporated

Inventor： Steven Bartling ,  Sudhanshu Khanna

IPC: H03K3/3562

CPC classification number: H03K3/35625

Abstract: In an embodiment of the invention, a flip-flop circuit contains a 2-input multiplexer, a master latch, a transfer gate and a slave latch. The scan enable control signals SE and SEN of the multiplexer determine whether data or scan data is input to the master latch. Clock signals CKT and CLKZ and retention control signals RET and RETN determine when the master latch is latched. The slave latch is configured to receive the output of the master latch, a second data bit D2, the clock signals CKT and CLKN, the retain control signals RET and RETN, the slave control signals SS and SSN. The signals CKT, CLKZ, RET, RETN, SS, SSN and PREN determine whether the output of the master latch or the second data bit D2 is latched in the slave latch. Control signals RET and RETN determine when data is stored in the slave latch during retention mode.

Abstract translation: 在本发明的实施例中，触发器电路包含2输入多路复用器，主锁存器，传输门和从锁存器。 复用器的扫描使能控制信号SE和SEN确定数据还是扫描数据被输入到主锁存器。 时钟信号CKT和CLKZ以及保持控制信号RET和RETN确定主锁存器何时被锁存。 从锁存器被配置为接收主锁存器的输出，第二数据位D2，时钟信号CKT和CLKN，保持控制信号RET和RETN，从控制信号SS和SSN。 信号CKT，CLKZ，RET，RETN，SS，SSN和PREN确定主锁存器或第二数据位D2的输出是否锁存在从锁存器中。 在保持模式期间，控制信号RET和RETN确定数据是否存储在从锁存器中。

公开(公告)号：US08803582B1

公开(公告)日：2014-08-12

申请号：US13875438

申请日：2013-05-02

Applicant: Texas Instruments Incorporated

Inventor： Steven Bartling ,  Sudhanshu Khanna

IPC: H03K3/289 ,  H03K3/037

CPC classification number: H03K3/35625

Abstract: In an embodiment of the invention, a flip-flop circuit contains a 2-input multiplexer, a master latch, a transfer gate and a slave latch. The scan enable control signals SE and SEN of the multiplexer determine whether data or scan data is input to the master latch. Clock signals CKT and CLKZ and retention control signals RET and RETN determine when the master latch is latched. The slave latch is configured to receive the output of the master latch, a second data bit D2, the clock signals CKT and CLN, the retain control signals RET and RETN, the slave control signals SS and SSN. The signals CKT, CLKZ, RET, RETN, SS, SSN and PREN determine whether the output of the master latch or the second data bit D2 is latched in the slave latch. Control signals RET and RETN determine when data is stored in the slave latch during retention mode.

Abstract translation: 在本发明的实施例中，触发器电路包含2输入多路复用器，主锁存器，传输门和从锁存器。 复用器的扫描使能控制信号SE和SEN确定数据还是扫描数据被输入到主锁存器。 时钟信号CKT和CLKZ以及保持控制信号RET和RETN确定主锁存器何时被锁存。 从锁存器被配置为接收主锁存器的输出，第二数据位D2，时钟信号CKT和CLN，保持控制信号RET和RETN，从控制信号SS和SSN。 信号CKT，CLKZ，RET，RETN，SS，SSN和PREN确定主锁存器或第二数据位D2的输出是否锁存在从锁存器中。 在保持模式期间，控制信号RET和RETN确定数据是否存储在从锁存器中。

公开(公告)号：US20140218090A1

公开(公告)日：2014-08-07

申请号：US13759240

申请日：2013-02-05

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Steven Bartling ,  Sudhanshu Khanna

IPC: H03K3/012

CPC classification number: H03K3/012 ,  H03K3/289 ,  H03K3/35625

Abstract: In an embodiment of the invention, a flip-flop circuit contains a 2-input multiplexer, a master latch, a transfer gate and a slave latch. The scan enable control signals SE and SEN of the multiplexer determine whether data or scan data is input to the master latch. The clock signals CLK and CLKN and retention control signals RET and RETN determine when the master latch is latched. The slave latch is configured to receive the output of the master latch, a second data bit D2, the clock signals CLK and CLN, the retain control signals RET and RETN, the slave control signals SS and SSN. The signals CLK, CLKN, RET, RETN, SS and SSN determine whether the output of the master latch or the second data bit D2 is latched in the slave latch. Control signals RET and RETN determine when data is stored in the slave latch during retention mode.

公开(公告)号：US20140211576A1

公开(公告)日：2014-07-31

申请号：US13753800

申请日：2013-01-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Steven Craig Bartling ,  Sudhanshu Khanna

IPC: G11C29/08

CPC classification number: G11C29/36 ,  G11C7/12 ,  G11C7/20 ,  G11C11/419 ,  G11C2029/1204

Abstract: A system on chip (SoC) provides a nonvolatile memory array that is configured as n rows by m columns of bit cells. Each of the bit cells is configured to store a bit of data. There are m bit lines each coupled to a corresponding one of the m columns of bit cells. There are m write drivers each coupled to a corresponding one of the m bit lines, wherein the m drivers each comprise a write one circuit and a write zero circuit. The m drivers are operable to write all ones into a row of bit cells in response to a first control signal coupled to the write one circuits and to write all zeros into a row of bit cells in response to a second control signal coupled to the write zero circuits.

Abstract translation: 片上系统（SoC）提供非易失性存储器阵列，其配置为n行x位的位单元。 每个位单元被配置为存储一位数据。 存在m个位线，每个位线耦合到位单元的m列的相应一个。 存在m个写入驱动器，每个m个驱动器都耦合到m个位线中的对应的一个，其中m个驱动器各自包括写入一个电路和写入零电路。 响应于耦合到写入一个电路的第一控制信号并且响应于耦合到写入的第二控制信号将全零写入位单元行中，m个驱动器可操作以将所有的一个写入一行位单元 零电路。

公开(公告)号：US20140211572A1

公开(公告)日：2014-07-31

申请号：US13753771

申请日：2013-01-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Steven Craig Bartling ,  Sudhanshu Khanna

IPC: G11C29/08

CPC classification number: G11C29/08 ,  G11C11/22 ,  G11C11/401 ,  G11C14/0072 ,  G11C29/02 ,  G11C29/12 ,  G11C29/34 ,  G11C29/50 ,  G11C29/50016 ,  G11C2029/0401

Abstract: A system on chip (SoC) provides a nonvolatile memory array that is configured as n rows by m columns of bit cells. Each of the bit cells is configured to store a bit of data. There are m bit lines each coupled to a corresponding one of the m columns of bit cells. There are m write drivers each coupled to a corresponding one of the m bit lines. An AND gate is coupled to the m bit lines and has an output line coupled to an input of a test controller on the SoC. An OR gate is coupled to the m bit lines and has an output line coupled to an input of the test controller.

Abstract translation: 片上系统（SoC）提供非易失性存储器阵列，其配置为n行x位的位单元。 每个位单元被配置为存储一位数据。 存在m个位线，每个位线耦合到位单元的m列的相应一个。 存在m个写入驱动器，每个写入驱动器耦合到m个位线中的相应一个位线。 与门耦合到m位线，并且具有耦合到SoC上的测试控制器的输入的输出线。 OR门耦合到m位线，并且具有耦合到测试控制器的输入的输出线。

公开(公告)号：US20140211533A1

公开(公告)日：2014-07-31

申请号：US13753814

申请日：2013-01-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sudhanshu Khanna ,  Steven Craig Bartling

IPC: G11C11/22

CPC classification number: G11C11/221

Abstract: A system on chip (SoC) provides a memory array of self referencing nonvolatile bitcells. Each bit cell includes two ferroelectric capacitors connected in series between a first plate line and a second plate line, such that a node Q is formed between the two ferroelectric capacitors. The first plate line and the second plate line are configured to provide a voltage approximately equal to first voltage while the bit cell is not being accessed. A clamping circuit coupled to the node Q. A first read capacitor is coupled to the bit line via a transfer device controlled by a first control signal. A second read capacitor coupled to the bit line via another transfer device controlled by a second control signal. A sense amp is coupled between the first read capacitor and the second read capacitor.

Abstract translation: 片上系统（SoC）提供了自参考非易失性位单元的存储器阵列。 每个位单元包括在第一板线和第二板线之间串联连接的两个铁电电容器，使得在两个铁电电容器之间形成节点Q。 第一板线和第二板线配置成在位单元未被访问时提供大致等于第一电压的电压。 耦合到节点Q的钳位电路。第一读取电容器经由由第一控制信号控制的传输装置耦合到位线。 通过由第二控制信号控制的另一转移装置耦合到位线的第二读电容器。 感测放大器耦合在第一读取电容器和第二读取电容器之间。

公开(公告)号：US20140210535A1

公开(公告)日：2014-07-31

申请号：US13753819

申请日：2013-01-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Steven Craig Bartling ,  Sudhanshu Khanna

IPC: H03K3/02

CPC classification number: H03K3/02 ,  G11C11/2275 ,  G11C11/419 ,  G11C14/0072 ,  H03K3/356104

Abstract: A system on chip (SoC) includes one or more core logic blocks that are configured to operate on a lower supply voltage and a memory array configured to operate on a higher supply voltage. Each bitcell in the memory has two ferroelectric capacitors connected in series between a first plate line and a second plate line to form a node Q. A data bit voltage is transferred to the node Q by activating a write driver to provide the data bit voltage responsive to the lower supply voltage. The data bit voltage is boosted on the node Q by activating a sense amp coupled to node Q of the selected bit cell, such that the sense amp senses the data bit voltage on the node Q and in response increases the data bit voltage on the node Q to the higher supply voltage.

Abstract translation: 片上系统（SoC）包括配置为在较低电源电压下操作的一个或多个核心逻辑块和配置为在较高电源电压下工作的存储器阵列。 存储器中的每个位单元具有串联连接在第一板线和第二板线之间以形成节点Q的两个铁电电容器。通过激活写驱动器将数据位电压传送到节点Q以提供数据位电压响应 到较低的电源电压。 通过激活耦合到所选位单元的节点Q的读出放大器，在节点Q上升高数据位电压，使得感测放大器感测节点Q上的数据位电压，并且响应于增加节点上的数据位电压 Q到更高的电源电压。