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    INTEGRATED CIRCUIT ISOLATION FEATURE AND METHOD OF FORMING THE SAME
    91.
    发明申请
    INTEGRATED CIRCUIT ISOLATION FEATURE AND METHOD OF FORMING THE SAME 有权

    公开(公告)号：US20220344199A1

    公开(公告)日：2022-10-27

    申请号：US17860264

    申请日：2022-07-08

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chih-Tang Peng ,  Shuen-Shin Liang ,  Keng-Chu Lin ,  Teng-Chun Tsai

    IPC: H01L21/762 ,  H01L21/8234 ,  H01L21/768 ,  H01L21/02

    Abstract: Examples of a technique for forming a dielectric material for an integrated circuit are provided herein. In an example, an integrated circuit workpiece is received that includes a recess. A first dielectric precursor is deposited in the recess. The first dielectric precursor includes a non-semiconductor component. A second dielectric precursor is deposited in the recess on the first dielectric precursor, and an annealing process is performed such that a portion of the non-semiconductor component of the first dielectric precursor diffuses into the second dielectric precursor. The non-semiconductor component may include oxygen, and the annealing process may be performed in one of a vacuum or an inert gas environment.

    METHOD AND STRUCTURE FOR BARRIER-LESS PLUG
    93.
    发明申请
    METHOD AND STRUCTURE FOR BARRIER-LESS PLUG 有权

    公开(公告)号：US20220108919A1

    公开(公告)日：2022-04-07

    申请号：US17509314

    申请日：2021-10-25

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Sung-Li Wang ,  Hung-Yi Huang ,  Yu-Yun Peng ,  Mrunal A. Khaderbad ,  Chia-Hung Chu ,  Shuen-Shin Liang ,  Keng-Chu Lin

    IPC: H01L21/768 ,  H01L21/265 ,  H01L23/532 ,  H01L23/535

    Abstract: A method includes receiving a structure having a dielectric layer over a conductive feature, wherein the conductive feature includes a second metal. The method further includes etching a hole through the dielectric layer and exposing the conductive feature and depositing a first metal into the hole and in direct contact with the dielectric layer and the conductive feature, wherein the first metal entirely fills the hole. The method further includes annealing the structure such that atoms of the second metal are diffused into grain boundaries of the first metal and into interfaces between the first metal and the dielectric layer. After the annealing, the method further includes performing a chemical mechanical planarization (CMP) process to remove at least a portion of the first metal.

    SPACER STRUCTURE FOR SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME
    94.
    发明申请
    SPACER STRUCTURE FOR SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME 有权

    公开(公告)号：US20220020644A1

    公开(公告)日：2022-01-20

    申请号：US17143698

    申请日：2021-01-07

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Han-Yu LIN ,  Jhih-Rong Huang ,  Yen-Tien Tung ,  Tzer-Min Shen ,  Fu-Ting Yen ,  Gary Chan ,  Keng-Chu Lin ,  Li-Te Lin ,  Pinyen Lin

    IPC: H01L21/8234 ,  H01L21/3065

    Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The method can include forming a fin structure over a substrate. The fin structure can include a first channel layer and a sacrificial layer. The method can further include forming a first recess structure in a first portion of the fin structure, forming a second recess structure in the sacrificial layer of a second portion of the fin structure, forming a dielectric layer in the first and second recess structures, and performing an oxygen-free cyclic etching process to etch the dielectric layer to expose the channel layer of the second portion of the fin structure. The process of performing the oxygen-free cyclic etching process can include performing a first etching process to selectively etch the dielectric layer over the channel layer of the second portion of the fin structure with a first etching selectivity, and performing a second etching process to selectively etch the dielectric layer over the channel layer of the second portion of fin structure with a second etching selectivity greater than the first etching selectivity

    Low Resistance Fill Metal Layer Material as Stressor in Metal Gates
    96.
    发明申请
    Low Resistance Fill Metal Layer Material as Stressor in Metal Gates 有权

    公开(公告)号：US20210183858A1

    公开(公告)日：2021-06-17

    申请号：US16717433

    申请日：2019-12-17

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Mrunal A Khaderbad ,  Ziwei Fang ,  Keng-Chu Lin ,  Hsueh Wen Tsau

    IPC: H01L27/092 ,  H01L21/8234 ,  H01L21/8238

    Abstract: An Integrated Circuit (IC) device includes a first plurality of semiconductor layers over a substrate, a first gate dielectric layer and a first gate electrode. The first gate electrode includes a first fill metal layer and a work function metal layer disposed between the first gate dielectric layer and the first fill metal layer. The IC device further includes a second plurality of semiconductor layers over the substrate, a second gate dielectric layer and a second gate electrode. The second gate electrode includes a second fill metal layer directly contacting the second gate dielectric layer. A top surface of the second fill metal layer extends above a topmost layer of the second plurality of semiconductor layers. The material of the semiconductor layers has a midgap. The work function metal layer has a work function lower than the midgap. The fill metal layer has a work function higher than the midgap.

    Device and method of dielectric layer
    98.
    发明授权
    Device and method of dielectric layer 有权

    公开(公告)号：US10957543B2

    公开(公告)日：2021-03-23

    申请号：US16015743

    申请日：2018-06-22

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Yu-Yun Peng ,  Chung-Chi Ko ,  Keng-Chu Lin

    IPC: H01L21/762 ,  H01L21/28 ,  H01L21/02

    Abstract: A method includes forming an interlayer dielectric (ILD) and a gate structure over a substrate. The gate structure is surrounded by the ILD. The gate structure is etched to form a recess. A first dielectric layer is deposited over sidewalls and a bottom of the recess and over a top surface of the ILD using a first Si-containing precursor. A second dielectric layer is deposited over and in contact with the first dielectric layer using a second Si-containing precursor different from the first Si-containing precursor. A third dielectric layer is deposited over and in contact with the second dielectric layer using the first Si-containing precursor. Portions of the first, second, and third dielectric layer over the top surface of the ILD are removed.

    Semiconductor device and manufacturing method thereof
    99.
    发明授权
    Semiconductor device and manufacturing method thereof 有权

    公开(公告)号：US10950714B2

    公开(公告)日：2021-03-16

    申请号：US16714532

    申请日：2019-12-13

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Kuo-Cheng Ching ,  Kuan-Lun Cheng ,  Chih-Hao Wang ,  Keng-Chu Lin ,  Shi-Ning Ju

    IPC: H01L29/06 ,  H01L21/8234 ,  H01L29/66 ,  H01L27/088 ,  H01L21/02 ,  H01L21/762

    Abstract: A semiconductor device includes a substrate, a first semiconductor fin and a second semiconductor fin, a gate structure, a shallow trench isolation (STI) oxide, and a dielectric layer. The first semiconductor fin and a second semiconductor fin extend upwardly from the substrate. The gate structure extends across the first and second semiconductor fins. The shallow trench isolation (STI) oxide has a horizontal portion extending along a top surface of the substrate and vertical portions extending upwardly from the horizontal portion along the first and second semiconductor fins. The dielectric layer has a horizontal portion extending along a top surface of the horizontal portion of the STI oxide and vertical portions extending upwardly from the horizontal portion of the dielectric layer to a position higher than top ends of the vertical portions of the STI oxide.

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