公开(公告)号：US20220344199A1

公开(公告)日：2022-10-27

申请号：US17860264

申请日：2022-07-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Tang Peng ,  Shuen-Shin Liang ,  Keng-Chu Lin ,  Teng-Chun Tsai

IPC: H01L21/762 ,  H01L21/8234 ,  H01L21/768 ,  H01L21/02

Abstract: Examples of a technique for forming a dielectric material for an integrated circuit are provided herein. In an example, an integrated circuit workpiece is received that includes a recess. A first dielectric precursor is deposited in the recess. The first dielectric precursor includes a non-semiconductor component. A second dielectric precursor is deposited in the recess on the first dielectric precursor, and an annealing process is performed such that a portion of the non-semiconductor component of the first dielectric precursor diffuses into the second dielectric precursor. The non-semiconductor component may include oxygen, and the annealing process may be performed in one of a vacuum or an inert gas environment.

公开(公告)号：US10943820B2

公开(公告)日：2021-03-09

申请号：US16414273

申请日：2019-05-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wan-Yi Kao ,  Wei-Jin Li ,  Chung-Chi Ko ,  Yu-Cheng Shiau ,  Han-Sheng Weng ,  Chih-Tang Peng ,  Tien-I Bao

IPC: H01L21/768 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/02 ,  H01L21/762

Abstract: A method for forming a semiconductor structure is provided. The method includes patterning a semiconductor substrate to form a first semiconductor fin and a second semiconductor fin adjacent to the first semiconductor fin, and depositing a first dielectric material on the first semiconductor fin and the second semiconductor fin on the semiconductor substrate using an atomic layer deposition process. There is a first trench between the first semiconductor fin and the second semiconductor fin. The method also includes filling the first trench with a flowable dielectric material, and heating the flowable dielectric material and the first dielectric material to form an isolation structure between the first semiconductor fin and the second semiconductor fin.

公开(公告)号：US09704974B2

公开(公告)日：2017-07-11

申请号：US14688885

申请日：2015-04-16

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chia-Wei Chang ,  An-Shen Chang ,  Eric Chih-Fang Liu ,  Ryan Chia-Jen Chen ,  Chia-Tai Lin ,  Chih-Tang Peng

IPC: H01L29/66 ,  H01L21/308

CPC classification number: H01L29/66795 ,  H01L21/3086

Abstract: A process of manufacturing a Fin-FET device, and the process includes following steps. An active fin structure and a dummy fin structure are formed from a substrate, and an isolation layer is covered over the active fin structure and the dummy fin structure. Then, the isolation layer above the dummy fin structure is removed, and the dummy fin structure is selectively etched, which a selective ratio of the dummy fin structure to the isolation layer is over 8.

公开(公告)号：US12170199B2

公开(公告)日：2024-12-17

申请号：US18362136

申请日：2023-07-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Je-Ming Kuo ,  Yen-Chun Huang ,  Chih-Tang Peng ,  Tien-I Bao

IPC: H01L21/02 ,  B05D3/06 ,  B05D7/00 ,  H01L21/311 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/06 ,  B05D1/00 ,  B05D1/38 ,  G03F7/16 ,  H01L21/768

Abstract: The present disclosure is generally related to semiconductor devices, and more particularly to a dielectric material formed in semiconductor devices. The present disclosure provides methods for forming a dielectric material layer by a cyclic spin-on coating process. In an embodiment, a method of forming a dielectric material on a substrate includes spin-coating a first portion of a dielectric material on a substrate, curing the first portion of the dielectric material on the substrate, spin-coating a second portion of the dielectric material on the substrate, and thermal annealing the dielectric material to form an annealed dielectric material on the substrate.

公开(公告)号：US20240186190A1

公开(公告)日：2024-06-06

申请号：US18152557

申请日：2023-01-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-I Lin ,  Cheng-Wei Chang ,  Ting-Hsiang Chang ,  Chih-Tang Peng ,  Yung-Cheng Lu

IPC: H01L21/8238 ,  H01L21/762 ,  H01L27/092

CPC classification number: H01L21/823878 ,  H01L21/76224 ,  H01L21/823821 ,  H01L27/0924

Abstract: In an embodiment, a method includes: forming a first fin and a second fin over a semiconductor substrate; forming an isolation region between the first fin and the second fin, forming the isolation region comprising: depositing an oxide liner along the first fin, the second fin, and the semiconductor substrate, the oxide liner comprising a first upper portion and a first lower portion along the first fin, the first lower portion being between the first upper portion and the semiconductor substrate; thinning the oxide liner; depositing an insulation material over the oxide liner; and recessing the insulation material; and forming a gate structure over the first fin, the second fin, and the isolation region.

公开(公告)号：US10937686B2

公开(公告)日：2021-03-02

申请号：US16517934

申请日：2019-07-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jian-Shiou Huang ,  Bang-Tai Tang ,  Chih-Tang Peng ,  Tai-Chun Huang ,  Yen-Chun Huang

IPC: H01L21/762 ,  H01L21/02 ,  H01L21/8234 ,  H01L21/84

Abstract: The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a semiconductor device having an enhanced gap fill layer in trenches. The present disclosure provides a novel gap fill layer formed using a multi-step deposition and in-situ treatment process. The deposition process can be a flowable chemical vapor deposition (FCVD) utilizing one or more assist gases and molecules of low reactive sticking coefficient (RSC). The treatment process can be an in-situ process after the deposition process and includes exposing the deposited gap fill layer to plasma activated assist gas. The assist gas can be formed of ammonia. The low RSC molecule can be formed of trisilylamin (TSA) or perhydropolysilazane (PHPS).

公开(公告)号：US10332746B1

公开(公告)日：2019-06-25

申请号：US15920753

申请日：2018-03-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： De-Wei Yu ,  Chien-Hao Chen ,  Chih-Tang Peng ,  Jei Ming Chen ,  Shu-Yi Wang

IPC: H01L21/02 ,  H01L21/28 ,  H01L29/66 ,  H01L21/3213 ,  H01L21/3205 ,  H01L21/8234 ,  H01L29/78

Abstract: Embodiments disclosed herein relate generally to forming a gate layer in high aspect ratio trenches using a cyclic deposition-etch process. In an embodiment, a method for semiconductor processing is provided. The method includes performing a first deposition process to form a conformal film over a bottom surface and along sidewall surfaces of a feature on a substrate. The method includes performing an etch process to remove a portion of the conformal film. The method includes repeating the first deposition process and the etch process to fill the feature with the conformal film. The method includes exposing the conformal film to ultraviolet light.

公开(公告)号：US09853102B2

公开(公告)日：2017-12-26

申请号：US14455598

申请日：2014-08-08

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Teng-Chun Tsai ,  Li-Ting Wang ,  Cheng-Tung Lin ,  De-Fang Chen ,  Chih-Tang Peng ,  Chien-Hsun Wang ,  Hung-Ta Lin

IPC: H01L29/08 ,  H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/66 ,  H01L21/265 ,  H01L29/51 ,  H01L29/739 ,  B82Y10/00 ,  H01L29/423 ,  H01L29/775 ,  H01L29/16

CPC classification number: H01L29/105 ,  B82Y10/00 ,  H01L21/265 ,  H01L21/823418 ,  H01L21/823462 ,  H01L21/823468 ,  H01L21/823487 ,  H01L21/823493 ,  H01L27/088 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/0847 ,  H01L29/1041 ,  H01L29/1608 ,  H01L29/42376 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66068 ,  H01L29/66356 ,  H01L29/66439 ,  H01L29/665 ,  H01L29/66553 ,  H01L29/66666 ,  H01L29/66977 ,  H01L29/7391 ,  H01L29/775 ,  H01L29/7827

Abstract: A tunnel field-effect transistor and method fabricating the same are provided. The tunnel field-effect transistor includes a drain region, a source region with opposite conductive type to the drain region, a channel region disposed between the drain region and the source region, a metal gate layer disposed around the channel region, and a high-k dielectric layer disposed between the metal gate layer and the channel region.

公开(公告)号：US12112974B2

公开(公告)日：2024-10-08

申请号：US17860264

申请日：2022-07-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Tang Peng ,  Shuen-Shin Liang ,  Keng-Chu Lin ,  Teng-Chun Tsai

IPC: H01L21/762 ,  H01L21/02 ,  H01L21/768 ,  H01L21/8234

CPC classification number: H01L21/76224 ,  H01L21/02164 ,  H01L21/02356 ,  H01L21/76826 ,  H01L21/76837 ,  H01L21/823481

Abstract: Examples of a technique for forming a dielectric material for an integrated circuit are provided herein. In an example, an integrated circuit workpiece is received that includes a recess. A first dielectric precursor is deposited in the recess. The first dielectric precursor includes a non-semiconductor component. A second dielectric precursor is deposited in the recess on the first dielectric precursor, and an annealing process is performed such that a portion of the non-semiconductor component of the first dielectric precursor diffuses into the second dielectric precursor. The non-semiconductor component may include oxygen, and the annealing process may be performed in one of a vacuum or an inert gas environment.

公开(公告)号：US20240204104A1

公开(公告)日：2024-06-20

申请号：US18591730

申请日：2024-02-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wan-Yi Kao ,  Yu-Cheng Shiau ,  Chunyao Wang ,  Chih-Tang Peng ,  Yung-Cheng Lu ,  Chi On Chui

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/762 ,  H01L21/8234 ,  H01L27/092 ,  H01L29/51 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L21/0214 ,  H01L21/02211 ,  H01L21/02263 ,  H01L21/76224 ,  H01L21/76232 ,  H01L21/823481 ,  H01L27/0924 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/66818 ,  H01L21/76227

Abstract: A semiconductor device and method of manufacture are provided. In embodiments a first liner is deposited to line a recess between a first semiconductor fin and a second semiconductor fin, the first liner comprising a first material. The first liner is annealed to transform the first material to a second material. A second liner is deposited to line the recess, the second liner comprising a third material. The second liner is annealed to transform the third material to a fourth material.