公开(公告)号：US11756864B2

公开(公告)日：2023-09-12

申请号：US17101158

申请日：2020-11-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Mrunal A Khaderbad ,  Yasutoshi Okuno ,  Sung-Li Wang ,  Pang-Yen Tsai ,  Shen-Nan Lee ,  Teng-Chun Tsai

IPC: H01L23/48 ,  H01L23/485 ,  H01L21/768 ,  H01L29/66 ,  H01L21/311 ,  H01L21/02 ,  H01L21/285 ,  H01L29/417 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/45 ,  H01L21/8238 ,  H01L23/532 ,  H01L23/528 ,  H01L29/08 ,  H01L29/41

CPC classification number: H01L23/485 ,  H01L21/02634 ,  H01L21/28562 ,  H01L21/31116 ,  H01L21/76814 ,  H01L21/76822 ,  H01L21/76826 ,  H01L21/76831 ,  H01L21/76846 ,  H01L21/76847 ,  H01L21/823431 ,  H01L21/823821 ,  H01L23/528 ,  H01L23/532 ,  H01L29/0847 ,  H01L29/41 ,  H01L29/417 ,  H01L29/41791 ,  H01L29/456 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7848

Abstract: A semiconductor device and a method of forming the same are provided. A method includes forming a gate over a semiconductor structure. An epitaxial source/drain region is formed adjacent the gate. A dielectric layer is formed over the epitaxial source/drain region. An opening extending through the dielectric layer and exposing the epitaxial source/drain region is formed. A conductive material is non-conformally deposited in the opening. The conductive material fills the opening in a bottom-up manner.

公开(公告)号：US20210183858A1

公开(公告)日：2021-06-17

申请号：US16717433

申请日：2019-12-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Mrunal A Khaderbad ,  Ziwei Fang ,  Keng-Chu Lin ,  Hsueh Wen Tsau

IPC: H01L27/092 ,  H01L21/8234 ,  H01L21/8238

Abstract: An Integrated Circuit (IC) device includes a first plurality of semiconductor layers over a substrate, a first gate dielectric layer and a first gate electrode. The first gate electrode includes a first fill metal layer and a work function metal layer disposed between the first gate dielectric layer and the first fill metal layer. The IC device further includes a second plurality of semiconductor layers over the substrate, a second gate dielectric layer and a second gate electrode. The second gate electrode includes a second fill metal layer directly contacting the second gate dielectric layer. A top surface of the second fill metal layer extends above a topmost layer of the second plurality of semiconductor layers. The material of the semiconductor layers has a midgap. The work function metal layer has a work function lower than the midgap. The fill metal layer has a work function higher than the midgap.

公开(公告)号：US11923367B2

公开(公告)日：2024-03-05

申请号：US17870964

申请日：2022-07-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Mrunal A Khaderbad ,  Ziwei Fang ,  Keng-Chu Lin ,  Hsueh Wen Tsau

IPC: H01L27/092 ,  H01L21/8234 ,  H01L21/8238

CPC classification number: H01L27/0924 ,  H01L21/823431 ,  H01L21/82345 ,  H01L21/823821 ,  H01L21/823842

Abstract: An integrated circuit (IC) device includes a semiconductor substrate having a first plurality of stacked semiconductor layers in a p-type transistor region and a second plurality of stacked semiconductor layers in a n-type transistor region. A gate dielectric layer wraps around each of the first and second plurality of stacked semiconductor layers. A first metal gate in the p-type transistor region has a work function metal layer and a first fill metal layer, where the work function metal layer wraps around and is in direct contact with the gate dielectric layer and the first fill metal layer is in direct contact with the work function metal layer. A second metal gate in the n-type transistor region has a second fill metal layer that is in direct contact with the gate dielectric layer, where the second fill metal layer has a work function about equal to or lower than 4.3 eV.

公开(公告)号：US20220384439A1

公开(公告)日：2022-12-01

申请号：US17870964

申请日：2022-07-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Mrunal A Khaderbad ,  Ziwei Fang ,  Keng-Chu Lin ,  Hsueh Wen Tsau

IPC: H01L27/092 ,  H01L21/8234 ,  H01L21/8238

Abstract: An integrated circuit (IC) device includes a semiconductor substrate having a first plurality of stacked semiconductor layers in a p-type transistor region and a second plurality of stacked semiconductor layers in a n-type transistor region. A gate dielectric layer wraps around each of the first and second plurality of stacked semiconductor layers. A first metal gate in the p-type transistor region has a work function metal layer and a first fill metal layer, where the work function metal layer wraps around and is in direct contact with the gate dielectric layer and the first fill metal layer is in direct contact with the work function metal layer. A second metal gate in the n-type transistor region has a second fill metal layer that is in direct contact with the gate dielectric layer, where the second fill metal layer has a work function about equal to or lower than 4.3 eV.