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    System, Device and Methods of Manufacture
    91.
    发明申请
    System, Device and Methods of Manufacture 有权

    公开(公告)号：US20220367267A1

    公开(公告)日：2022-11-17

    申请号：US17870075

    申请日：2022-07-21

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chen-Hua Yu ,  Wei Ling Chang ,  Chuei-Tang Wang ,  Tin-Hao Kuo ,  Che-Wei Hsu

    IPC: H01L21/768 ,  H01L23/00 ,  H01L21/77 ,  H01L23/528 ,  H01L25/18

    Abstract: Systems, devices and methods of manufacturing a system on silicon wafer (SoSW) device and package are described herein. A plurality of functional dies is formed in a silicon wafer. Different sets of masks are used to form different types of the functional dies in the silicon wafer. A first redistribution structure is formed over the silicon wafer and provides local interconnects between adjacent dies of the same type and/or of different types. A second redistribution structure may be formed over the first redistribution layer and provides semi-global and/or global interconnects between non-adjacent dies of the same type and/or of different types. An optional backside redistribution structure may be formed over a second side of the silicon wafer opposite the first redistribution layer. The optional backside redistribution structure may provide backside interconnects between functional dies of different types.

    Packages with Thick RDLs and Thin RDLs Stacked Alternatingly
    92.
    发明申请
    Packages with Thick RDLs and Thin RDLs Stacked Alternatingly 有权

    公开(公告)号：US20220359403A1

    公开(公告)日：2022-11-10

    申请号：US17814730

    申请日：2022-07-25

    Applicant: Taiwan Semiconductor Manufacturing Co,. Ltd.

    Inventor： Po-Yuan Teng ,  Kuo Lung Pan ,  Yu-Chia Lai ,  Tin-Hao Kuo ,  Hao-Yi Tsai ,  Chen-Hua Yu

    IPC: H01L23/538 ,  H01L23/00 ,  H01L23/552 ,  H01L21/48

    Abstract: A method includes forming a plurality of dielectric layers, which processes include forming a first plurality of dielectric layers having first thicknesses, and forming a second plurality of dielectric layers having second thicknesses smaller than the first thicknesses. The first plurality of dielectric layers and the second plurality of dielectric layers are laid out alternatingly. The method further includes forming a plurality of redistribution lines connected to form a conductive path, which processes include forming a first plurality of redistribution lines, each being in one of the first plurality of dielectric layers, and forming a second plurality of redistribution lines, each being in one of the second plurality of dielectric layers.

    Chip package and method of forming the same
    96.
    发明授权
    Chip package and method of forming the same 有权

    公开(公告)号：US11201118B2

    公开(公告)日：2021-12-14

    申请号：US16874672

    申请日：2020-05-14

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Kuo-Lung Pan ,  Hao-Yi Tsai ,  Tin-Hao Kuo

    IPC: H01L23/538 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L21/48 ,  H01L23/29 ,  H01L23/48 ,  H01L23/15 ,  H01L23/28 ,  H01L23/522 ,  H01L23/14 ,  H01L23/528

    Abstract: A chip package including a first semiconductor die, a support structure and a second semiconductor die is provided. The first semiconductor die includes a first dielectric layer and a plurality of conductive vias, the first dielectric layer includes a first region and a second region, the conductive vias is embedded in the first region of the first dielectric layer; a plurality of conductive pillars is disposed on and electrically connected to the conductive vias. The second semiconductor die is stacked over the support structure and the second region of the first dielectric layer; and an insulating encapsulant encapsulates the first semiconductor die, the second semiconductor die, the support structure and the conductive pillars, wherein the second semiconductor die is electrically connected to the first semiconductor die through the conductive pillars.

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