公开(公告)号：US20210242159A1

公开(公告)日：2021-08-05

申请号：US16897296

申请日：2020-06-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Yuan Teng ,  Hao-Yi Tsai ,  Kuo-Lung Pan ,  Sen-Kuei Hsu ,  Tin-Hao Kuo ,  Yi-Yang Lei ,  Ying-Cheng Tseng ,  Chi-Hui Lai

IPC: H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H01L23/538 ,  H01L21/48 ,  H01L21/683

Abstract: A package structure including at least one semiconductor die and a redistribution structure is provided. The semiconductor die is laterally encapsulated by an encapsulant, and the redistribution structure is disposed on the semiconductor die and the encapsulant and electrically connected with the semiconductor die. The redistribution structure includes signal lines and a pair of repair lines. The signal lines include a pair of first signal lines located at a first level, and each first signal line of the pair of first signal lines has a break that split each first signal line into separate first and second fragments. The pair of repair lines is located above the pair of first signal lines and located right above the break. Opposite ending portions of each repair line are respectively connected with the first and second fragments with each repair line covering the break in each first signal line.

公开(公告)号：US20210020538A1

公开(公告)日：2021-01-21

申请号：US16515024

申请日：2019-07-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Wei Chen ,  Hao-Yi Tsai ,  Kuo-Lung Pan ,  Tin-Hao Kuo ,  Po-Yuan Teng ,  Chi-Hui Lai

IPC: H01L23/367 ,  H01L21/48 ,  H01L21/3205 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L23/498

Abstract: A package structure includes a semiconductor die, a redistribution circuit structure, and a metallization element. The semiconductor die has an active side and an opposite side opposite to the active side. The redistribution circuit structure is disposed on the active side and is electrically coupled to the semiconductor die. The metallization element has a plate portion and a branch portion connecting to the plate portion, wherein the metallization element is electrically isolated to the semiconductor die, and the plate portion of the metallization element is in contact with the opposite side.

公开(公告)号：US20240371726A1

公开(公告)日：2024-11-07

申请号：US18778763

申请日：2024-07-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shu-Rong Chun ,  Kuo-Lung Pan ,  Pei-Hsuan Lee ,  Chien Ling Hwang ,  Yu-Chia Lai ,  Tin-Hao Kuo ,  Hao-Yi Tsai ,  Chen-Hua Yu

IPC: H01L23/40 ,  H01L23/00

Abstract: In an embodiment, a device includes: a package component including integrated circuit dies, an encapsulant around the integrated circuit dies, a redistribution structure over the encapsulant and the integrated circuit dies, and sockets over the redistribution structure; a mechanical brace physically coupled to the sockets, the mechanical brace having openings, each one of the openings exposing a respective one of the sockets; a thermal module physically and thermally coupled to the encapsulant and the integrated circuit dies; and bolts extending through the thermal module, the mechanical brace, and the package component.

公开(公告)号：US20230307375A1

公开(公告)日：2023-09-28

申请号：US18151583

申请日：2023-01-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hao-Cheng Hou ,  Tsung-Ding Wang ,  Jung Wei Cheng ,  Yu-Min Liang ,  Chien-Hsun Lee ,  Shang-Yun Hou ,  Wei-Yu Chen ,  Collin Jordon Fleshman ,  Kuo-Lung Pan ,  Shu-Rong Chun ,  Sheng-Chi Lin

IPC: H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L25/00 ,  H10B80/00 ,  H01L25/18 ,  H01L21/56 ,  H01L23/48

CPC classification number: H01L23/5385 ,  H01L23/3121 ,  H01L24/19 ,  H01L24/20 ,  H01L25/50 ,  H10B80/00 ,  H01L25/18 ,  H01L21/561 ,  H01L23/481 ,  H01L23/562 ,  H01L2224/16227 ,  H01L24/16 ,  H01L24/29 ,  H01L2224/2929 ,  H01L2924/0665 ,  H01L2224/29386 ,  H01L2924/05442 ,  H01L2924/05432 ,  H01L2924/0503 ,  H01L24/32 ,  H01L2224/32225 ,  H01L24/73 ,  H01L2224/73204 ,  H01L2224/19 ,  H01L2224/211

Abstract: A method includes forming a composite package substrate. The formation of the composite package substrate includes encapsulating an interconnect die in an encapsulant, with the interconnect die including a plurality of through-vias therein, and forming a first plurality of redistribution lines (RDLs) and a second plurality of RDLs on opposite sides of the interconnect die. The method further includes bonding an organic package substrate to the composite package substrate, and bonding a first package component and a second package component to the first plurality of RDLs. The first package component and the second package component are electrically interconnected through the interconnect die and the first plurality of RDLs.

公开(公告)号：US11355466B2

公开(公告)日：2022-06-07

申请号：US16897296

申请日：2020-06-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Yuan Teng ,  Hao-Yi Tsai ,  Kuo-Lung Pan ,  Sen-Kuei Hsu ,  Tin-Hao Kuo ,  Yi-Yang Lei ,  Ying-Cheng Tseng ,  Chi-Hui Lai

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H01L21/48 ,  H01L21/683

Abstract: A package structure including at least one semiconductor die and a redistribution structure is provided. The semiconductor die is laterally encapsulated by an encapsulant, and the redistribution structure is disposed on the semiconductor die and the encapsulant and electrically connected with the semiconductor die. The redistribution structure includes signal lines and a pair of repair lines. The signal lines include a pair of first signal lines located at a first level, and each first signal line of the pair of first signal lines has a break that split each first signal line into separate first and second fragments. The pair of repair lines is located above the pair of first signal lines and located right above the break. Opposite ending portions of each repair line are respectively connected with the first and second fragments with each repair line covering the break in each first signal line.

公开(公告)号：US11239135B2

公开(公告)日：2022-02-01

申请号：US16515024

申请日：2019-07-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Wei Chen ,  Hao-Yi Tsai ,  Kuo-Lung Pan ,  Tin-Hao Kuo ,  Po-Yuan Teng ,  Chi-Hui Lai

IPC: H01L23/367 ,  H01L21/48 ,  H01L21/3205 ,  H01L25/065 ,  H01L23/373 ,  H01L23/552 ,  H01L23/00 ,  H01L25/18 ,  H01L23/498

Abstract: A package structure includes a semiconductor die, a redistribution circuit structure, and a metallization element. The semiconductor die has an active side and an opposite side opposite to the active side. The redistribution circuit structure is disposed on the active side and is electrically coupled to the semiconductor die. The metallization element has a plate portion and a branch portion connecting to the plate portion, wherein the metallization element is electrically isolated to the semiconductor die, and the plate portion of the metallization element is in contact with the opposite side.

公开(公告)号：US10658258B1

公开(公告)日：2020-05-19

申请号：US16281094

申请日：2019-02-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Lung Pan ,  Hao-Yi Tsai ,  Tin-Hao Kuo

IPC: H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L23/538 ,  H01L21/48 ,  H01L23/29 ,  H01L23/48 ,  H01L23/15 ,  H01L23/28 ,  H01L23/522 ,  H01L23/14 ,  H01L23/528

Abstract: A chip package including a first semiconductor die, a support structure and a second semiconductor die is provided. The first semiconductor die includes a first dielectric layer and a plurality of conductive vias, the first dielectric layer includes a first region and a second region, the conductive vias is embedded in the first region of the first dielectric layer; a plurality of conductive pillars is disposed on and electrically connected to the conductive vias. The second semiconductor die is stacked over the support structure and the second region of the first dielectric layer; and an insulating encapsulant encapsulates the first semiconductor die, the second semiconductor die, the support structure and the conductive pillars, wherein the second semiconductor die is electrically connected to the first semiconductor die through the conductive pillars.

公开(公告)号：US10461023B2

公开(公告)日：2019-10-29

申请号：US15884357

申请日：2018-01-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Mao-Yen Chang ,  Hao-Yi Tsai ,  Kuo-Lung Pan ,  Tin-Hao Kuo ,  Tzung-Hui Lee ,  Teng-Yuan Lo ,  Hao-Chun Ting

IPC: H01L23/498 ,  H01L23/31 ,  H01L21/48 ,  H01L25/10

Abstract: Semiconductor package s and methods of forming the same are disclosed. The semiconductor package includes a chip, a redistribution circuit structure and a UBM pattern. The redistribution circuit structure is disposed over and electrically connected to the chip and includes a topmost conductive pattern. The UBM pattern is disposed over and electrically connected to the topmost conductive pattern, wherein the UBM pattern includes a set of vias and a pad on the set of vias, wherein the vias are arranged in an array and electrically connected to the pad and the topmost conductive pattern.

公开(公告)号：US20230178536A1

公开(公告)日：2023-06-08

申请号：US17655835

申请日：2022-03-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Mao-Yen Chang ,  Yu-Chia Lai ,  Kuo-Lung Pan ,  Cheng-Shiuan Wong ,  Hsiu-Jen Lin ,  Ching-Hua Hsieh

IPC: H01L25/00 ,  H01L25/065 ,  H01L23/00 ,  H01L21/56 ,  H01L21/683

CPC classification number: H01L25/50 ,  H01L25/0655 ,  H01L25/0652 ,  H01L24/19 ,  H01L24/20 ,  H01L21/568 ,  H01L21/6836 ,  H01L24/81 ,  H01L24/16 ,  H01L2224/2105 ,  H01L2224/16146 ,  H01L24/32 ,  H01L2224/32245 ,  H01L24/73 ,  H01L2224/73267 ,  H01L24/83

Abstract: A method includes forming a reconstructed wafer, which includes placing a plurality of device dies over a carrier, encapsulating the plurality of device dies in an encapsulant, and forming a redistribution structure over the plurality of device dies and the encapsulant. The redistribution structure includes a plurality of dielectric layers and a plurality of redistribution lines in the plurality of dielectric layers. The method further includes performing a trimming process on the reconstructed wafer. The trimming process forms a round edge for the reconstructed wafer. A sawing process is performed on the reconstructed wafer, so that the reconstructed wafer includes straight edges.

公开(公告)号：US11444002B2

公开(公告)日：2022-09-13

申请号：US16941541

申请日：2020-07-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Chia Lai ,  Chen-Hua Yu ,  Chung-Shi Liu ,  Hsiao-Chung Liang ,  Hao-Yi Tsai ,  Chien-Ling Hwang ,  Kuo-Lung Pan ,  Pei-Hsuan Lee ,  Tin-Hao Kuo ,  Chih-Hsuan Tai

IPC: H01L23/40 ,  H01L23/58 ,  H01L25/18 ,  H01L23/00

Abstract: A package structure includes a bottom plate, a semiconductor package, a top plate, a screw and an anti-loosening coating. The semiconductor package is disposed over the bottom plate. The top plate is disposed over the semiconductor package, and includes an internal thread in a screw hole of the top plate. The screw penetrates through the bottom plate, the semiconductor package and the top plate, and includes an external thread. The external thread of the screw is engaged to the internal thread of the top plate, and the anti-loosening coating is adhered between the external thread and the internal thread.