公开(公告)号：US11984372B2

公开(公告)日：2024-05-14

申请号：US17875656

申请日：2022-07-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Teng-Yuan Lo ,  Lipu Kris Chuang ,  Hsin-Yu Pan

IPC: H01L23/24 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/00 ,  H01L25/065 ,  H01L25/10

CPC classification number: H01L23/24 ,  H01L21/4846 ,  H01L21/561 ,  H01L23/3135 ,  H01L23/3185 ,  H01L23/49827 ,  H01L24/16 ,  H01L24/81 ,  H01L24/97 ,  H01L25/0655 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/16145 ,  H01L2224/81815 ,  H01L2225/1035 ,  H01L2225/1058

Abstract: A package structure and a method of forming the same are provided. A method includes forming first electrical connectors and second electrical connectors on a first side of an interposer wafer. An integrated circuit die is bonded to the first side of the interposer wafer using the first electrical connectors. A stiffener structure is attached to the first side of the interposer wafer adjacent the integrated circuit die. The stiffener structure covers the second electrical connectors in a plan view. The integrated circuit die and the stiffener structure are encapsulated with a first encapsulant. The interposer wafer and the stiffener structure are singulated to form a stacked structure.

公开(公告)号：US20220068736A1

公开(公告)日：2022-03-03

申请号：US17162073

申请日：2021-01-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Teng-Yuan Lo ,  Lipu Kris Chuang ,  Hsin-Yu Pan

IPC: H01L23/24 ,  H01L21/56 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L23/31 ,  H01L23/498 ,  H01L25/10 ,  H01L21/48

Abstract: A package structure and a method of forming the same are provided. A method includes forming first electrical connectors and second electrical connectors on a first side of an interposer wafer. An integrated circuit die is bonded to the first side of the interposer wafer using the first electrical connectors. A stiffener structure is attached to the first side of the interposer wafer adjacent the integrated circuit die. The stiffener structure covers the second electrical connectors in a plan view. The integrated circuit die and the stiffener structure are encapsulated with a first encapsulant. The interposer wafer and the stiffener structure are singulated to form a stacked structure.

公开(公告)号：US20210296221A1

公开(公告)日：2021-09-23

申请号：US16827595

申请日：2020-03-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ching-Feng Yang ,  Hsin-Yu Pan ,  Kai-Chiang Wu ,  Chien-Chang Lin

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/52 ,  H01L23/16

Abstract: A semiconductor package includes a circuit board structure, a redistribution layer structure, a package structure, and a ring structure. The redistribution layer structure has a first region and a second region surrounding the first region. The redistribution layer structure is disposed over and electrically connected to the circuit board structure. A metal density in the second region is greater than a metal density in the first region. The package structure is disposed over the first region of the redistribution layer structure. The package structure is electrically connected to the redistribution layer structure. The ring structure is disposed over the second region of the redistribution layer structure.

公开(公告)号：US10818588B2

公开(公告)日：2020-10-27

申请号：US16262924

申请日：2019-01-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sen-Kuei Hsu ,  Hsin-Yu Pan ,  Yi-Che Chiang

IPC: H01L23/10 ,  H01L23/34 ,  H01L23/522 ,  H01L23/31 ,  H01L23/36 ,  H01L23/00 ,  H01L23/528 ,  H01L21/48 ,  H01L21/56

Abstract: A package structure includes a semiconductor die, an insulating encapsulant, a first redistribution layer, a second redistribution layer, a heat dissipation element and conductive balls. The insulating encapsulant is encapsulating the semiconductor die, and has a first surface and a second surface opposite to the first surface. The first redistribution layer is located on the first surface of the insulating encapsulant and includes at least one feed line and one ground plate. The second redistribution layer is located on the second surface of the insulating encapsulant and electrically connected to the semiconductor die and the first redistribution layer. The heat dissipation element is disposed on the first redistribution layer and includes a conductive base and antenna patterns, wherein the antenna patterns is electrically connected to the feed line and is electrically coupled to the ground plate of the first redistribution layer.

公开(公告)号：US20200251414A1

公开(公告)日：2020-08-06

申请号：US16262924

申请日：2019-01-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sen-Kuei Hsu ,  Hsin-Yu Pan ,  Yi-Che Chiang

IPC: H01L23/522 ,  H01L23/31 ,  H01L23/36 ,  H01L23/00 ,  H01L23/528 ,  H01L21/48 ,  H01L21/56

Abstract: A package structure includes a semiconductor die, an insulating encapsulant, a first redistribution layer, a second redistribution layer, a heat dissipation element and conductive balls. The insulating encapsulant is encapsulating the semiconductor die, and has a first surface and a second surface opposite to the first surface. The first redistribution layer is located on the first surface of the insulating encapsulant and includes at least one feed line and one ground plate. The second redistribution layer is located on the second surface of the insulating encapsulant and electrically connected to the semiconductor die and the first redistribution layer. The heat dissipation element is disposed on the first redistribution layer and includes a conductive base and antenna patterns, wherein the antenna patterns is electrically connected to the feed line and is electrically coupled to the ground plate of the first redistribution layer.

公开(公告)号：US20200135692A1

公开(公告)日：2020-04-30

申请号：US16713009

申请日：2019-12-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Wei Chen ,  Chih-Hua Chen ,  Hsin-Yu Pan ,  Hao-Yi Tsai ,  Lipu Kris Chuang ,  Tin-Hao Kuo

IPC: H01L23/00 ,  H01L25/00 ,  H01L21/56 ,  H01L25/065 ,  H01L23/31 ,  H01L23/538 ,  H01L23/373 ,  H01L23/367

Abstract: A semiconductor package includes a redistribution structure, at least one semiconductor device, a heat dissipation component, and an encapsulating material. The at least one semiconductor device is disposed on and electrically connected to the redistribution structure. The heat dissipation component is disposed on the redistribution structure and includes a concave portion for receiving the at least one semiconductor device and an extending portion connected to the concave portion and contacting the redistribution structure, wherein the concave portion contacts the at least one semiconductor device. The encapsulating material is disposed over the redistribution structure, wherein the encapsulating material fills the concave portion and encapsulates the at least one semiconductor device.

公开(公告)号：US20240136280A1

公开(公告)日：2024-04-25

申请号：US18401815

申请日：2024-01-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chao-Wen Shih ,  Chen-Hua Yu ,  Han-Ping Pu ,  Hsin-Yu Pan ,  Hao-Yi Tsai ,  Sen-Kuei Hsu

IPC: H01L23/525 ,  H01L21/56 ,  H01L23/00 ,  H01L23/29 ,  H01L23/31 ,  H01L23/522 ,  H01L23/532 ,  H01L23/552

CPC classification number: H01L23/525 ,  H01L21/56 ,  H01L23/293 ,  H01L23/3192 ,  H01L23/5225 ,  H01L23/5329 ,  H01L23/552 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/14 ,  H01L23/5286 ,  H01L24/13

Abstract: A method includes forming a dielectric layer over a contact pad of a device, forming a first polymer layer over the dielectric layer, forming a first conductive line and a first portion of a second conductive line over the first polymer layer, patterning a photoresist to form an opening over the first portion of the second conductive feature, wherein after patterning the photoresist the first conductive line remains covered by photoresist, forming a second portion of the second conductive line in the opening, wherein the second portion of the second conductive line physically contacts the first portion of the second conductive line, and forming a second polymer layer extending completely over the first conductive line and the second portion of the second conductive line.

公开(公告)号：US11705378B2

公开(公告)日：2023-07-18

申请号：US16933910

申请日：2020-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jung-Wei Cheng ,  Jiun-Yi Wu ,  Hsin-Yu Pan ,  Tsung-Ding Wang ,  Yu-Min Liang ,  Wei-Yu Chen

IPC: H01L23/31 ,  H01L23/40 ,  H01L23/538

CPC classification number: H01L23/3135 ,  H01L23/4012 ,  H01L23/5383

Abstract: A semiconductor package includes a circuit board structure, a first redistribution layer structure and first bonding elements. The circuit board structure includes outermost first conductive patterns and a first mask layer adjacent to the outermost first conductive patterns. The first redistribution layer structure is disposed over the circuit board structure. The first bonding elements are disposed between and electrically connected to the first redistribution layer structure and the outermost first conductive patterns of the circuit board structure. In some embodiments, at least one of the first bonding elements covers a top and a sidewall of the corresponding outermost first conductive pattern.

公开(公告)号：US11551999B2

公开(公告)日：2023-01-10

申请号：US16897300

申请日：2020-06-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Lipu Kris Chuang ,  Chung-Shi Liu ,  Han-Ping Pu ,  Hsin-Yu Pan ,  Ming-Kai Liu ,  Ting-Chu Ko

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/48 ,  H01L23/31 ,  H01L21/56 ,  H01L21/48 ,  H01L23/367

Abstract: A memory device including a base chip and a memory cube mounted on and connected with the base chip is described. The memory cube includes multiple stacked tiers, and each tier of the multiple stacked tiers includes semiconductor chips laterally wrapped by an encapsulant and a redistribution structure. The semiconductor chips of the multiple stacked tiers are electrically connected with the base chip through the redistribution structures in the multiple stacked tiers. The memory cube includes a thermal path structure extending through the multiple stacked tiers and connected to the base chip. The thermal path structure has a thermal conductivity larger than that of the encapsulant. The thermal path structure is electrically isolated from the semiconductor chips in the multiple stacked tiers and the base chip.

公开(公告)号：US11532576B2

公开(公告)日：2022-12-20

申请号：US16787020

申请日：2020-02-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sen-Kuei Hsu ,  Hsin-Yu Pan ,  Yi-Che Chiang

IPC: H01L21/66 ,  H01L27/146 ,  H01L23/00 ,  G01R31/28

Abstract: A manufacturing method of a semiconductor package includes the following steps. Semiconductor chips are disposed on a carrier. The semiconductor chips are grouped in a plurality of package units. The semiconductor chips are encapsulated in an encapsulant to form a reconstructed wafer. A redistribution structure is formed on the encapsulant. The redistribution structure electrically connects the semiconductor chips within a same package unit of the plurality of package units. The individual package units are separated by cutting through the reconstructed wafer along scribe line regions. In the reconstructed wafer, the plurality of package units are arranged so as to balance the number of scribe line regions extending across opposite halves of the reconstructed wafer in a first direction with respect to the number of scribe line regions extending across opposite halves of the reconstructed wafer in a second direction perpendicular to the first direction.