公开(公告)号：US10606596B2

公开(公告)日：2020-03-31

申请号：US16203528

申请日：2018-11-28

Applicant: Texas Instruments Incorporated

Inventor： Joseph Raymond Michael Zbiciak ,  Timothy David Anderson ,  Jonathan (Son) Hung Tran ,  Kai Chirca ,  Daniel Wu ,  Abhijeet Ashok Chachad ,  David M. Thompson

IPC: G06F9/34 ,  G06F9/312 ,  G06F11/00 ,  G06F12/02 ,  G06F9/30 ,  G06F9/345 ,  G06F12/0875 ,  G06F9/38 ,  G06F9/32 ,  G06F12/0897 ,  G06F11/10 ,  G06F12/0862 ,  G06F12/1036

Abstract: A stream of data is accessed from a memory system using a stream of addresses generated in a first mode of operating a streaming engine in response to executing a first stream instruction. A block cache preload operation is performed on a cache in the memory using a block of addresses generated in a second mode of operating the streaming engine in response to executing a second stream instruction.

公开(公告)号：US10599433B2

公开(公告)日：2020-03-24

申请号：US16203503

申请日：2018-11-28

Applicant: Texas Instruments Incorporated

Inventor： Joseph Raymond Michael Zbiciak ,  Timothy David Anderson ,  Jonathan (Son) Hung Tran ,  Kai Chirca ,  Daniel Wu ,  Abhijeet Ashok Chachad ,  David M. Thompson

IPC: G06F9/312 ,  G06F9/34 ,  G06F11/00 ,  G06F12/02 ,  G06F9/30 ,  G06F9/345 ,  G06F12/0875 ,  G06F9/38 ,  G06F9/32 ,  G06F12/0897 ,  G06F11/10 ,  G06F12/0831 ,  G06F12/1027 ,  G06F12/0862

Abstract: A stream of data is accessed from a memory system using a stream of addresses generated in a first mode of operating a streaming engine in response to executing a first stream instruction. A block cache management operation is performed on a cache in the memory using a block of addresses generated in a second mode of operating the streaming engine in response to executing a second stream instruction.

公开(公告)号：US20200089495A1

公开(公告)日：2020-03-19

申请号：US16580490

申请日：2019-09-24

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Timothy David Anderson ,  Duc Quang Bui ,  Peter Richard Dent

IPC: G06F9/30

Abstract: Disclosed embodiments relate to methods of using a processor to load and duplicate scalar data from a source into a destination register. The data may be duplicated in byte, half word, word or double word parts, according to a duplication pattern.

公开(公告)号：US20190391812A1

公开(公告)日：2019-12-26

申请号：US16558569

申请日：2019-09-03

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Timothy David Anderson ,  Duc Quang Bui ,  Joseph Raymond Michael Zbiciak

IPC: G06F9/38 ,  G06F9/30

Abstract: In one embodiment, a system includes a memory and a processor core. The processor core includes functional units and an instruction decode unit configured to determine whether an execute packet of instructions received by the processing core includes a first instruction that is designated for execution by a first functional unit of the functional units and a second instruction that is a condition code extension instruction that includes a plurality of sets of condition code bits, wherein each set of condition code bits corresponds to a different one of the functional units, and wherein the sets of condition code bits include a first set of condition code bits that corresponds to the first functional unit. When the execute packet includes the first and second instructions, the first functional unit is configured to execute the first instruction conditionally based upon the first set of condition code bits in the second instruction.

公开(公告)号：US20190278598A1

公开(公告)日：2019-09-12

申请号：US16420480

申请日：2019-05-23

Applicant: Texas Instruments Incorporated

Inventor： Asheesh Bhardwaj ,  Timothy David Anderson ,  Son Hung Tran

IPC: G06F9/30 ,  G06F9/345 ,  G06F9/38 ,  G06F11/10 ,  G06F9/32 ,  G06F12/0875 ,  G06F12/0897 ,  G06F11/00

Abstract: Software instructions are executed on a processor within a computer system to configure a steaming engine with stream parameters to define a multidimensional array. The stream parameters define a size for each dimension of the multidimensional array and a pad value indicator. Data is fetched from a memory coupled to the streaming engine responsive to the stream parameters. A stream of vectors is formed for the multidimensional array responsive to the stream parameters from the data fetched from memory. A padded stream vector is formed that includes a specified pad value without accessing the pad value from system memory.

公开(公告)号：US20190278597A1

公开(公告)日：2019-09-12

申请号：US16420467

申请日：2019-05-23

Applicant: Texas Instruments Incorporated

Inventor： Asheesh Bhardwaj ,  William Franklin Leven ,  Son Hung Tran ,  Timothy David Anderson

IPC: G06F9/30 ,  G06F9/345 ,  G06F9/38 ,  G06F11/10 ,  G06F9/32 ,  G06F12/0875 ,  G06F12/0897 ,  G06F11/00

Abstract: Software instructions are executed on a processor within a computer system to configure a steaming engine with stream parameters to define a multidimensional array. The stream parameters define a size for each dimension of the multidimensional array, a null vector count (N), and a selected dimension. Data is fetched from a memory coupled to the streaming engine responsive to the stream parameters. A stream of vectors is formed for the multidimensional array responsive to the stream parameters from the data fetched from memory. N null stream vectors are inserted into the stream of vectors for the selected dimension without fetching respective null data from the memory.

公开(公告)号：US20190138307A1

公开(公告)日：2019-05-09

申请号：US16236936

申请日：2018-12-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Timothy David Anderson ,  Duc Quang Bui

IPC: G06F9/30 ,  G06F9/38 ,  G06F1/3206 ,  G06F1/3287

Abstract: In one disclosed embodiment, a processor includes a first execution unit and a second execution unit, a register file, and a data path including a plurality of lanes. The data path and the register file are arranged so that writing to the register file by the first execution unit and by the second execution unit is allowed over the data path, reading from the register file by the first execution unit is allowed over the data path, and reading from the register file by the second execution unit is not allowed over the data path. The processor also includes a power control circuit configured to, when a transfer of data between the register file and either of the first and second execution units uses less than all of the lanes, power down the lanes of the data path not used for the transfer of the data.

公开(公告)号：US20180300133A1

公开(公告)日：2018-10-18

申请号：US16018234

申请日：2018-06-26

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Timothy David Anderson ,  Duc Quang Bui ,  Mel Alan Phipps ,  Todd T. Hahn ,  Joseph Zbiciak

IPC: G06F9/30

Abstract: The number of registers required is reduced by overlapping scalar and vector registers. This allows increased compiler flexibility when mixing scalar and vector instructions. Local register read ports are reduced by restricting read access. Dedicated predicate registers reduce requirements for general registers, and allows reduction of critical timing paths by allowing the predicate registers to be placed next to the predicate unit.

公开(公告)号：US20170115990A1

公开(公告)日：2017-04-27

申请号：US14920298

申请日：2015-10-22

Applicant: Texas Instruments Incorporated

Inventor： Timothy David Anderson ,  Duc Quang Bui ,  Joseph Raymond Michael Zbiciak

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3802 ,  G06F9/30072 ,  G06F9/30076 ,  G06F9/3013 ,  G06F9/30145 ,  G06F9/30185 ,  G06F9/3822 ,  G06F9/3853 ,  G06F9/3891

Abstract: One embodiment of this invention provides two conditional execution auxiliary instructions directed to disparate subsets of the plural functional units. Depending on the conditional execution desired, only one of the two conditional execution auxiliary instructions may be required for a particular execute packet. Another embodiment of this invention employs only one of two possible register files for the condition registers. In a VLIW processor it may be advantageous to split the functional units into separate sets with corresponding register files. This limits the number of functional units that may simultaneously access the register files. In the preferred embodiment of this invention the functional units are divided into a scalar set which access scalar registers and a vector set which access vector registers. The data registers storing the conditions for both scalar and vector instructions are in the scalar data register file.

公开(公告)号：US09489197B2

公开(公告)日：2016-11-08

申请号：US14327022

申请日：2014-07-09

Applicant: Texas Instruments Incorporated

Inventor： Mujibur Rahman ,  Peter Richard Dent ,  Timothy David Anderson ,  Duc Quang Bui

IPC: G06F17/15 ,  G06F9/30 ,  G06F9/38

CPC classification number: G06F9/3001 ,  G06F9/30036 ,  G06F9/30094 ,  G06F9/3013 ,  G06F9/3853 ,  G06F9/3895 ,  G06F17/15

Abstract: This invention is a digital signal processor capable of performing correlation of data with pseudo noise for code division multiple access (CDMA) decoding using clusters. Each cluster includes plural multipliers. The multipliers multiply real and imaginary parts of packed data by corresponding pseudo noise data. Within a cluster the real parts and the imaginary parts of the products are summed separately. This forms plural complex number outputs equal in number to the number of clusters. The pseudo noise data is offset relative to the data input differing amounts for different clusters. The clusters are divided into first half clusters receiving data from even numbered slots and second half clusters receiving data from odd numbered slots. The correlation unit includes a mask input to selectively zero a multiplier product.

Abstract translation: 本发明是一种数字信号处理器，能够执行数据与伪噪声的相关，以便使用簇进行码分多址（CDMA）解码。 每个簇包括多个乘法器。 乘法器将打包数据的实部和虚部乘以相应的伪噪声数据。 在集群中，产品的实部和虚部分别相加。 这形成数量与簇数相等的多个复数输出。 伪噪声数据相对于数据输入偏移不同的簇的不同量。 这些簇被分成从偶数编号的时隙接收数据的第一个半组和从奇数编号的时隙接收数据的第二个半组。 相关单元包括用于选择性地使乘法器乘积为零的掩码输入。