公开(公告)号：US08004892B2

公开(公告)日：2011-08-23

申请号：US12632121

申请日：2009-12-07

申请人： Tommaso Vali ,  Giovanni Santin ,  Michele Incarnati

发明人： Tommaso Vali ,  Giovanni Santin ,  Michele Incarnati

IPC分类号： G11C11/34

CPC分类号： G11C7/1051 ,  G11C7/106 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/28 ,  G11C2211/5642 ,  G11C2211/5647

摘要： A single latch circuit is coupled to each bit line in a multiple level cell memory device to handle reading multiple data bits. The circuit is comprised of a latch having an inverted node and a non-inverted node. A first control transistor selectively couples the non-inverted node to a latch output. A second control transistor selectively couples the inverted node to the latch output. A reset transistor is coupled between the inverted node and circuit ground to selectively ground the circuit when the transistor is turned on.

摘要翻译： 单个锁存电路耦合到多电平单元存储器件中的每个位线，以处理读取多个数据位。 该电路由具有反向节点和非反相节点的锁存器组成。 第一控制晶体管选择性地将非反相节点耦合到锁存器输出。 第二控制晶体管选择性地将反相节点耦合到锁存器输出。 复位晶体管耦合在反相节点和电路接地之间，以在晶体管导通时有选择地接地电路。

公开(公告)号：US20100259992A1

公开(公告)日：2010-10-14

申请号：US12820430

申请日：2010-06-22

申请人： Giovanni Santin ,  Michele Incarnati

发明人： Giovanni Santin ,  Michele Incarnati

IPC分类号： G11C16/04

CPC分类号： G11C16/3418

摘要： Methods and apparatus for programming a memory cell using one or more blocking memory cells facilitate mitigation of capacitive voltage coupling. The methods include applying a program voltage to a selected memory cell of a string of memory cells, and applying a cutoff voltage to a set of one or more memory cells of the string between the selected memory cell and a select gate. The methods further include applying a pass voltage to one or more other memory cells of the string between the selected memory cell and the select gate. Other methods further include applying other pass voltages, other cutoff voltages and/or intermediate voltages to still other memory cells of the string.

摘要翻译： 使用一个或多个阻塞存储器单元来编程存储器单元的方法和装置有助于缓解电容性电压耦合。 所述方法包括将程序电压施加到存储器单元串的所选择的存储单元，以及将所述截止电压施加到所选存储单元和选择栅极之间的所述串的一个或多个存储单元的集合。 所述方法还包括将通过电压施加到所选择的存储器单元和选择栅极之间的串的一个或多个其它存储单元。 其他方法还包括将其他通过电压，其它截止电压和/或中间电压应用于串的其他存储单元。

公开(公告)号：US20100085807A1

公开(公告)日：2010-04-08

申请号：US12632121

申请日：2009-12-07

申请人： Tommaso Vali ,  Giovanni Santin ,  Michele Incarnati

发明人： Tommaso Vali ,  Giovanni Santin ,  Michele Incarnati

IPC分类号： G11C16/04 ,  G11C7/10 ,  G11C16/06

CPC分类号： G11C7/1051 ,  G11C7/106 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/28 ,  G11C2211/5642 ,  G11C2211/5647

摘要： A single latch circuit is coupled to each bit line in a multiple level cell memory device to handle reading multiple data bits. The circuit is comprised of a latch having an inverted node and a non-inverted node. A first control transistor selectively couples the non-inverted node to a latch output. A second control transistor selectively couples the inverted node to the latch output. A reset transistor is coupled between the inverted node and circuit ground to selectively ground the circuit when the transistor is turned on.

摘要翻译： 单个锁存电路耦合到多电平单元存储器件中的每个位线，以处理读取多个数据位。 该电路由具有反向节点和非反相节点的锁存器组成。 第一控制晶体管选择性地将非反相节点耦合到锁存器输出。 第二控制晶体管选择性地将反相节点耦合到锁存器输出。 复位晶体管耦合在反相节点和电路接地之间，以在晶体管导通时有选择地接地电路。

公开(公告)号：US20100054068A1

公开(公告)日：2010-03-04

申请号：US12613114

申请日：2009-11-05

申请人： Michele Incarnati ,  Giovanni Santin

发明人： Michele Incarnati ,  Giovanni Santin

IPC分类号： G11C7/04

CPC分类号： G11C7/04 ,  G11C5/143

摘要： A temperature sensor generates a digital representation of the temperature of the integrated circuit. A logic circuit reads the digital temperature and generates a multiple bit digital representation of an operational voltage and a multiple bit digital representation of a timing signal, both being functions of the integrated circuit temperature. A voltage generator converts the digital representation of the operational voltage to an analog voltage that biases portions of the integrated circuit requiring temperature compensated voltages. In one embodiment, the temperature compensated voltages bias memory cells. A timing generator converts the multiple bit digital representation of the timing signal to a logic signal.

摘要翻译： 温度传感器产生集成电路的温度的数字表示。 逻辑电路读取数字温度并产生作为集成电路温度的函数的定时信号的工作电压和多位数字表示的多位数字表示。 电压发生器将操作电压的数字表示转换为模拟电压，该模拟电压偏置需要温度补偿电压的集成电路的部分。 在一个实施例中，温度补偿电压偏置存储器单元。 定时发生器将定时信号的多位数字表示转换为逻辑信号。

公开(公告)号：US07466602B2

公开(公告)日：2008-12-16

申请号：US11758373

申请日：2007-06-05

申请人： Tommaso Vali ,  Giovanni Santin ,  Michele Incarnati

发明人： Tommaso Vali ,  Giovanni Santin ,  Michele Incarnati

IPC分类号： G11C7/10

CPC分类号： G11C7/1051 ,  G11C7/02 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1069 ,  G11C7/22 ,  G11C2207/2281

摘要： Apparatus and methods for filtering spurious output transitions with an adaptive filtering circuit which tracks the memory architecture and form factors with a reduced speed penalty. The filtering is selectable by a fuse option.

摘要翻译： 用自适应滤波电路滤波杂散输出转换的装置和方法，该自适应滤波电路以降低的速度损失跟踪存储器架构和形状因子。 滤波可由保险丝选项选择。

公开(公告)号：US20080266953A1

公开(公告)日：2008-10-30

申请号：US12170563

申请日：2008-07-10

申请人： Tommaso Vali ,  Giovanni Santin ,  Michele Incarnati

发明人： Tommaso Vali ,  Giovanni Santin ,  Michele Incarnati

IPC分类号： G11C7/10 ,  G11C16/04

CPC分类号： G11C7/1051 ,  G11C7/106 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/28 ,  G11C2211/5642 ,  G11C2211/5647

摘要： A single latch circuit is coupled to each bit line in a multiple level cell memory device to handle reading multiple data bits. The circuit is comprised of a latch having an inverted node and a non-inverted node. A first control transistor selectively couples the non-inverted node to a latch output. A second control transistor selectively couples the inverted node to the latch output. A reset transistor is coupled between the inverted node and circuit ground to selectively ground the circuit when the transistor is turned on.

摘要翻译： 单个锁存电路耦合到多电平单元存储器件中的每个位线，以处理读取多个数据位。 该电路由具有反向节点和非反相节点的锁存器组成。 第一控制晶体管选择性地将非反相节点耦合到锁存器输出。 第二控制晶体管选择性地将反相节点耦合到锁存器输出。 复位晶体管耦合在反相节点和电路接地之间，以在晶体管导通时有选择地接地电路。

公开(公告)号：US20070189071A1

公开(公告)日：2007-08-16

申请号：US11506428

申请日：2006-08-18

申请人： Tommaso Vali ,  Giovanni Santin ,  Michele Incarnati

发明人： Tommaso Vali ,  Giovanni Santin ,  Michele Incarnati

IPC分类号： G11C14/00 ,  G11C16/04 ,  G11C7/10 ,  G11C11/34

CPC分类号： G11C7/1051 ,  G11C7/106 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/28 ,  G11C2211/5642 ,  G11C2211/5647

摘要： A single latch circuit is coupled to each bit line in a multiple level cell memory device to handle reading multiple data bits. The circuit is comprised of a latch having an inverted node and a non-inverted node. A first control transistor selectively couples the non-inverted node to a latch output. A second control transistor selectively couples the inverted node to the latch output. A reset transistor is coupled between the inverted node and circuit ground to selectively ground the circuit when the transistor is turned on.

摘要翻译： 单个锁存电路耦合到多电平单元存储器件中的每个位线，以处理读取多个数据位。 该电路由具有反向节点和非反相节点的锁存器组成。 第一控制晶体管选择性地将非反相节点耦合到锁存器输出。 第二控制晶体管选择性地将反相节点耦合到锁存器输出。 复位晶体管耦合在反相节点和电路接地之间，以在晶体管导通时有选择地接地电路。

公开(公告)号：US07113435B2

公开(公告)日：2006-09-26

申请号：US11127599

申请日：2005-05-12

申请人： Giovanni Santin

发明人： Giovanni Santin

IPC分类号： G11C7/00

CPC分类号： G11C29/1201 ,  G11C29/40

摘要： Memory devices having a normal mode of operation and a test mode of operation are useful in quality programs. The test mode of operation includes a data compression test mode. In the data compression test mode, reading one word of an output page provides an indication of the data values of the remaining words of the output page. The time necessary to read and verify a repeating test pattern can be reduced as only one word of each output page need be read to determine the ability of the memory device to accurately write and store data values. The memory devices include data compression circuits to compare data values for each bit location of each word of the output page. Output is selectively disabled if a bit location for one word of the output page has a data value differing from any remaining word of the output page.

公开(公告)号：US06847574B2

公开(公告)日：2005-01-25

申请号：US10196602

申请日：2002-07-15

申请人： Giovanni Santin

发明人： Giovanni Santin

IPC分类号： G11C16/06 ,  G11C29/00 ,  G11C29/04 ,  H01L21/82 ,  G11C11/00

CPC分类号： G11C29/70

摘要： An enhanced fuse circuit is discussed that advances redundancy techniques in integrated circuits. The enhanced fuse circuit uses a single nonvolatile fuse and a latch that is coupled at a desired time. One embodiment of the invention discusses a fuse circuit that includes a volatile latch and a nonvolatile fuse. The nonvolatile fuse adapts to operate with a voltage supply greater than about 1.65 volts. The voltage supply is boosted at a desired time to a predetermined level and for a predetermined duration so that the nonvolatile fuse transfers its data to the volatile latch.

摘要翻译： 讨论了一种增强型熔丝电路，用于提高集成电路中的冗余技术。 增强熔丝电路使用单个非易失性熔丝和在期望时间耦合的锁存器。 本发明的一个实施例讨论了包括易失性锁存器和非易失性熔断器的熔丝电路。 非易失性熔断器适用于大于1.65伏特的电源。 电压源在期望的时间被提升到预定电平并达预定的持续时间，使得非易失性熔丝将其数据传送到易失性锁存器。

公开(公告)号：US06845029B2

公开(公告)日：2005-01-18

申请号：US10642959

申请日：2003-08-18

申请人： Giovanni Santin ,  Giovanni Naso

发明人： Giovanni Santin ,  Giovanni Naso

IPC分类号： G11C16/20 ,  G11C16/26 ,  G11C17/18 ,  G11C29/00 ,  G11C17/00

CPC分类号： G11C29/789 ,  G11C16/0441 ,  G11C16/20 ,  G11C16/26 ,  G11C17/18

摘要： Fuse circuits based on a single flash cell or floating-gate memory cell are adapted for use in memory devices, particularly in low-voltage, flash memory applications. The fuse circuits include a floating-gate memory cell for storing a data value and a fuse latch to hold and transfer the data value of the floating-gate memory cell at power-up or upon request. A latch driver circuit can write data values to the fuse latch without affecting the data value stored in the floating-gate memory cell. The fuse circuits can further utilize the same structure, pitch, bit-line organization and word-line organization as the memory device's memory array. As the fuse circuits can utilize the same structure and organization, the data value of the fuse circuit can be programmed, erased and read using the same data path as the regular memory array.

摘要翻译： 基于单个闪存单元或浮动栅极存储单元的保险丝电路适用于存储器件，特别是在低电压闪速存储器应用中。 熔丝电路包括用于存储数据值的浮动栅存储器单元和用于在通电或根据要求保持和传送浮栅存储单元的数据值的熔丝锁存器。 锁存驱动器电路可以将数据值写入熔丝锁存器而不影响存储在浮动栅极存储单元中的数据值。 熔丝电路可以进一步利用与存储器件的存储器阵列相同的结构，间距，位线组织和字线组织。 由于熔丝电路可以使用相同的结构和组织，因此可以使用与常规存储器阵列相同的数据路径对熔丝电路的数据值进行编程，擦除和读取。