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91.发明授权Selective application of voltages for testing storage cells in semiconductor memory arrangements 失效选择性地应用电压以测试半导体存储器布置中的存储单元
公开(公告)号：US4839865A
公开(公告)日：1989-06-13
申请号：US934666
申请日：1986-11-24
IPC分类号： G11C11/401 , G11C11/404 , G11C11/4074 , G11C29/00 , G11C29/50
CPC分类号： G11C29/50016 , G11C11/4074 , G11C29/50 , G11C11/401 , G11C2029/5004
摘要： A dynamic RAM is provided with a plurality of 1-MOSFET memory cells, each having a storage capacitor and a switching MOSFET coupled to one electrode of the storage capacitor. The other electrode of each of the storage capacitors is coupled to a switching circuit which controls the voltage which is applied to the capacitor. The switching circuit is, in turn, coupled to both a voltage generating circuit (which preferably provides a voltage of 1/2 Vcc) and a voltage supply circuit which is set to provide predetermined test voltages. Thus, by operating the switching circuit, a voltage of 1/2 Vcc can be applied to the memory cell capacitors during normal operation of the dynamic RAM, and the predetermined test voltages can be applied to the memory cell capacitors during a testing operation.
摘要翻译： 动态RAM设置有多个1-MOSFET存储单元，每个具有存储电容器和耦合到存储电容器的一个电极的开关MOSFET。 每个存储电容器的另一个电极耦合到控制施加到电容器的电压的开关电路。 开关电路又耦合到电压产生电路（其优选地提供1/2Vcc的电压）和被设置为提供预定测试电压的电压供应电路两者。 因此，通过操作开关电路，在动态RAM的正常操作期间可以向存储单元电容器施加1/2Vcc的电压，并且可以在测试操作期间将预定的测试电压施加到存储单元电容器。
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92.发明授权
公开(公告)号：US4775959A
公开(公告)日：1988-10-04
申请号：US763615
申请日：1985-08-08
IPC分类号： G11C11/407 , G11C5/14 , G11C11/4074 , G11C7/00 , G11C11/40
CPC分类号： G11C5/146 , G11C11/4074
摘要： In typical MOS integrated circuit devices, the level of the back-bias voltage which is generated by a built-in back-bias generation circuit and is supplied to a semiconductor substrate is changed by an undesirable leakage current flowing through the semiconductor substrate. The leakage current is not constant. Instead, it becomes relatively small when a main circuit formed on the semiconductor substrate such as a dynamic RAM is not operative, and relatively great when such a circuit is operative. To reduce the change of the back-bias voltage resulting from the change of the leakage current, a back-bias voltage generation circuit is provided which has output capacity of a plurality of levels. Its output capacity is increased in response to an operation control signal of the main circuit. The level change of the back-bias voltage generation circuit can further be reduced by providing a level detection circuit for detecting the level change and a feedback circuit for controlling the back-bias voltage generation circuit in accordance with the output of the level detection circuit.
摘要翻译： 在典型的MOS集成电路器件中，内置反向偏置产生电路产生并提供给半导体衬底的背偏电压的电平由于流过半导体衬底的不期望的漏电流而改变。 漏电流不是恒定的。 相反，当形成在诸如动态RAM的半导体衬底上的主电路不可操作时，其变得相对较小，并且当这种电路工作时相对较大。 为了减少由漏电流的变化引起的背偏电压的变化，提供了具有多个电平的输出容量的背偏压产生电路。 其输出容量响应于主电路的操作控制信号而增加。 根据电平检测电路的输出，通过提供用于检测电平变化的电平检测电路和用于控制反偏压产生电路的反馈电路，可以进一步降低背偏压产生电路的电平变化。
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公开(公告)号：US08222945B2
公开(公告)日：2012-07-17
申请号：US13253584
申请日：2011-10-05
IPC分类号： H03L5/00
CPC分类号： H03K19/0016 , H01L23/5286 , H01L27/0207 , H01L27/092 , H01L27/0928 , H01L27/11898 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A semiconductor integrated circuit device provided with a first circuit block BLK1, a second circuit block DRV1 and a conversion circuit MIO1 for connecting the first circuit block to the second circuit block. The first circuit block includes a first mode for applying a supply voltage and a second mode for shutting off the supply voltage. The conversion circuit is provided with a function for maintaining the potential of an input node of the second circuit block at an operation potential, thereby suppressing a penetrating current flow when the first circuit block is in the second mode. The conversion circuit (MIO1 to MIO4) are commonly used for connecting circuit blocks.
摘要翻译： 具有第一电路块BLK1，第二电路块DRV1和用于将第一电路块连接到第二电路块的转换电路MIO1的半导体集成电路器件。 第一电路块包括用于施加电源电压的第一模式和用于关断电源电压的第二模式。 转换电路具有将第二电路块的输入节点的电位维持在操作电位的功能，从而当第一电路块处于第二模式时抑制穿透电流流动。 转换电路（MIO1〜MIO4）通常用于连接电路块。
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公开(公告)号：US08093723B2
公开(公告)日：2012-01-10
申请号：US13098648
申请日：2011-05-02
申请人： Takako Funakoshi , Eiichi Murakami , Kazumasa Yanagisawa , Kan Takeuchi , Hideo Aoki , Hizuru Yamaguchi , Takayuki Oshima , Kazuyuki Tsunokuni , Kousuke Okuyama
发明人： Takako Funakoshi , Eiichi Murakami , Kazumasa Yanagisawa , Kan Takeuchi , Hideo Aoki , Hizuru Yamaguchi , Takayuki Oshima , Kazuyuki Tsunokuni , Kousuke Okuyama
CPC分类号： H01L23/53238 , H01L21/823871 , H01L23/5286 , H01L2924/0002 , H01L2924/00
摘要： In a semiconductor integrated circuit device having plural layers of buried wirings, it is intended to prevent the occurrence of a discontinuity caused by stress migration at an interface between a plug connected at a bottom thereof to a buried wiring and the buried wiring. For example, in the case where the width of a first Cu wiring is not smaller than about 0.9 μm and is smaller than about 1.44 μm, and the width of a second Cu wiring and the diameter of a plug are about 0.18 μm, there are arranged two or more plugs which connect the first wirings and the second Cu wirings electrically with each other.
摘要翻译： 在具有多层埋地布线的半导体集成电路器件中，旨在防止在其底部连接到埋地布线的插头与埋地布线之间的界面处的应力迁移引起的不连续性的发生。 例如，在第一Cu布线的宽度不小于约0.9μm且小于约1.44μm的情况下，并且第二Cu布线的宽度和塞子的直径为约0.18μm的情况下，存在 布置两个或更多个将第一布线和第二铜布线彼此电连接的插头。
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公开(公告)号：US20110128780A1
公开(公告)日：2011-06-02
申请号：US13024252
申请日：2011-02-09
IPC分类号： G11C11/00
CPC分类号： G11C13/004 , G11C7/04 , G11C13/0004 , G11C13/0069 , G11C2013/0054 , G11C2013/0092 , G11C2213/79
摘要： At the time of, for example, a set operation (SET) for making a phase-change element in a crystalline state, a pulse of a voltage Vreset required for melting the element is applied to the phase-change element, and subsequently a pulse of a voltage Vset that is lower than Vreset and is required for crystallizing the element is applied thereto. And, the magnitude of this voltage Vset is then changed depending on the ambient temperature so that the magnitude of the voltage Vset is small as the temperature becomes high (TH). In this manner, a margin of a write operation between the set operation and a reset operation (RESET) for making the element to be in amorphous state is improved.
摘要翻译： 在例如用于使相变元件处于结晶状态的设定操作（SET）时，将元件熔化所需的电压Vreset的脉冲施加到相变元件，随后将脉冲 的电压Vset低于Vreset，并且是将元件结晶所需要的。 而且，该电压Vset的大小然后根据环境温度而改变，使得随着温度变高（TH），电压Vset的大小较小。 以这种方式，提高了设置操作和用于使元件处于非晶态的复位操作（RESET）之间的写入操作余量。
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公开(公告)号：US20110068826A1
公开(公告)日：2011-03-24
申请号：US12957462
申请日：2010-12-01
IPC分类号： H03K19/0175
CPC分类号： G11C5/147
摘要： A semiconductor integrated circuit device enhanced in design efficiency while achieving multi-functionalization and power saving is to be provided. The semiconductor integrated circuit device has first through third circuit blocks, and is placed in a first power supply state in which the operation of internal circuits in the first circuit block is guaranteed in accordance with an instruction from the third circuit block or a second power supply state in which the operation of the internal circuits is not guaranteed. The second circuit block has an input unit which receives signals supplied from the first circuit block, and the input unit of the second circuit block has an input circuit which, in accordance with a control signal sent from said third circuit block to said second circuit block, causes a specific signal level to be maintained in compliance with the operating voltage of the second circuit block irrespective of the signal supplied from the first circuit block when the third circuit block instructs the second power supply state to the first circuit block.
摘要翻译： 提供一种在实现多功能化和省电的同时提高设计效率的半导体集成电路装置。 半导体集成电路装置具有第一至第三电路块，并且被置于第一电源状态，其中根据来自第三电路块或第二电源的指令保证第一电路块中的内部电路的操作 不能保证内部电路的运行状态。 第二电路块具有接收从第一电路块提供的信号的输入单元，并且第二电路块的输入单元具有输入电路，该输入电路根据从所述第三电路块发送到所述第二电路块的控制信号 当第三电路块向第一电路块指示第二电源状态时，使得与第二电路块的工作电压保持一定的特定信号电平，而与第一电路块所提供的信号无关。
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公开(公告)号：US07907435B2
公开(公告)日：2011-03-15
申请号：US11915126
申请日：2005-09-21
IPC分类号： G11C11/00
CPC分类号： G11C13/004 , G11C7/04 , G11C13/0004 , G11C13/0069 , G11C2013/0054 , G11C2013/0092 , G11C2213/79
摘要： At the time of, for example, a set operation (SET) for making a phase-change element in a crystalline state, a pulse of a voltage Vreset required for melting the element is applied to the phase-change element, and subsequently a pulse of a voltage Vset that is lower than Vreset and is required for crystallizing the element is applied thereto. And, the magnitude of this voltage Vset is then changed depending on the ambient temperature so that the magnitude of the voltage Vset is small as the temperature becomes high (TH). In this manner, a margin of a write operation between the set operation and a reset operation (RESET) for making the element to be in amorphous state is improved.
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公开(公告)号：US07612601B2
公开(公告)日：2009-11-03
申请号：US11783920
申请日：2007-04-13
IPC分类号： H03L5/00
CPC分类号： H03K19/0016 , H01L23/5286 , H01L27/0207 , H01L27/092 , H01L27/0928 , H01L27/11898 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A semiconductor integrated circuit device provided with a first circuit block BLK1, a second circuit block DRV1 and a conversion circuit MIO1 for connecting the first circuit block to the second circuit block. The first circuit block includes a first mode for applying a supply voltage and a second mode for shutting off the supply voltage. The conversion circuit is provided with a function for maintaining the potential of an input node of the second circuit block at an operation potential, thereby suppressing a penetrating current flow when the first circuit block is in the second mode. The conversion circuit (MIO1 to MIO4) are commonly used for connecting circuit blocks.
摘要翻译： 具有第一电路块BLK1，第二电路块DRV1和用于将第一电路块连接到第二电路块的转换电路MIO1的半导体集成电路器件。 第一电路块包括用于施加电源电压的第一模式和用于关断电源电压的第二模式。 转换电路具有将第二电路块的输入节点的电位维持在操作电位的功能，从而当第一电路块处于第二模式时抑制穿透电流流动。 转换电路（MIO1〜MIO4）通常用于连接电路块。
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公开(公告)号：US20090073753A1
公开(公告)日：2009-03-19
申请号：US11915126
申请日：2005-09-21
IPC分类号： G11C11/00
CPC分类号： G11C13/004 , G11C7/04 , G11C13/0004 , G11C13/0069 , G11C2013/0054 , G11C2013/0092 , G11C2213/79
摘要： At the time of, for example, a set operation (SET) for making a phase-change element in a crystalline state, a pulse of a voltage Vreset required for melting the element is applied to the phase-change element, and subsequently a pulse of a voltage Vset that is lower than Vreset and is required for crystallizing the element is applied thereto. And, the magnitude of this voltage Vset is then changed depending on the ambient temperature so that the magnitude of the voltage Vset is small as the temperature becomes high (TH). In this manner, a margin of a write operation between the set operation and a reset operation (RESET) for making the element to be in amorphous state is improved.
摘要翻译： 在例如用于使相变元件处于结晶状态的设定操作（SET）时，将元件熔化所需的电压Vreset的脉冲施加到相变元件，随后将脉冲 的电压Vset低于Vreset，并且是将元件结晶所需要的。 而且，该电压Vset的大小然后根据环境温度而改变，使得随着温度变高（TH），电压Vset的大小较小。 以这种方式，提高了设置操作和用于使元件处于非晶态的复位操作（RESET）之间的写入操作余量。
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公开(公告)号：US20080279000A1
公开(公告)日：2008-11-13
申请号：US12172889
申请日：2008-07-14
摘要： There is provided a high-density mask ROM operable at a high speed. With the mask ROM, respective source lines are disposed so as to be shared by memory cells in respective columns adjacent to each other, and bit lines are disposed so as to correspond to the respective columns of the memory cells. Further, the dummy cells are disposed for the respective columns of the memory cells. The dummy cells are each made up of a series-circuit including a first switching transistor that is turned into the conducting state in response to a signal potential on a dummy word line (DWL), and a second switching transistor 17 for coupling an adjacent source line to the bit line corresponding thereto in response to a potential of the source line in a column corresponding thereto. The memory cells each are made up of one unit of a transistor and a data storage formed by mask wiring. At the time of reading data, a potential of the source line in a select column is caused to undergo a change, whereupon there occurs a potential difference between a pair made up of the bit line as selected to which the memory cells as selected are coupled, and a reference bit line with the dummy cells coupled thereto, so that it is possible to execute readout of data by detecting the potential difference.
摘要翻译： 提供了可高速操作的高密度掩模ROM。 利用掩模ROM，各个源极线被布置成由彼此相邻的各个列中的存储单元共享，并且位线被布置为与存储单元的各个列对应。 此外，为存储单元的各列设置虚设单元。 虚拟单元各自由串联电路组成，串联电路包括响应于虚拟字线（DWL）上的信号电位而变为导通状态的第一开关晶体管，以及用于耦合相邻源极的第二开关晶体管17 响应于与其对应的列中的源极线的电位，对应于其的位线。 每个存储单元由晶体管的一个单元和由掩模布线形成的数据存储器构成。 在读取数据时，使选择列中的源极线的电位发生变化，由此选择由所选择的存储器单元耦合到的位线构成的一对之间存在电位差 以及与其耦合的虚拟单元的参考位线，使得可以通过检测电位差来执行数据的读出。
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