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公开(公告)号：US20110128780A1
公开(公告)日：2011-06-02
申请号：US13024252
申请日：2011-02-09
IPC分类号： G11C11/00
CPC分类号： G11C13/004 , G11C7/04 , G11C13/0004 , G11C13/0069 , G11C2013/0054 , G11C2013/0092 , G11C2213/79
摘要： At the time of, for example, a set operation (SET) for making a phase-change element in a crystalline state, a pulse of a voltage Vreset required for melting the element is applied to the phase-change element, and subsequently a pulse of a voltage Vset that is lower than Vreset and is required for crystallizing the element is applied thereto. And, the magnitude of this voltage Vset is then changed depending on the ambient temperature so that the magnitude of the voltage Vset is small as the temperature becomes high (TH). In this manner, a margin of a write operation between the set operation and a reset operation (RESET) for making the element to be in amorphous state is improved.
摘要翻译： 在例如用于使相变元件处于结晶状态的设定操作（SET）时，将元件熔化所需的电压Vreset的脉冲施加到相变元件，随后将脉冲 的电压Vset低于Vreset，并且是将元件结晶所需要的。 而且，该电压Vset的大小然后根据环境温度而改变，使得随着温度变高（TH），电压Vset的大小较小。 以这种方式，提高了设置操作和用于使元件处于非晶态的复位操作（RESET）之间的写入操作余量。
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公开(公告)号：US07907435B2
公开(公告)日：2011-03-15
申请号：US11915126
申请日：2005-09-21
IPC分类号： G11C11/00
CPC分类号： G11C13/004 , G11C7/04 , G11C13/0004 , G11C13/0069 , G11C2013/0054 , G11C2013/0092 , G11C2213/79
摘要： At the time of, for example, a set operation (SET) for making a phase-change element in a crystalline state, a pulse of a voltage Vreset required for melting the element is applied to the phase-change element, and subsequently a pulse of a voltage Vset that is lower than Vreset and is required for crystallizing the element is applied thereto. And, the magnitude of this voltage Vset is then changed depending on the ambient temperature so that the magnitude of the voltage Vset is small as the temperature becomes high (TH). In this manner, a margin of a write operation between the set operation and a reset operation (RESET) for making the element to be in amorphous state is improved.
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公开(公告)号：US20090073753A1
公开(公告)日：2009-03-19
申请号：US11915126
申请日：2005-09-21
IPC分类号： G11C11/00
CPC分类号： G11C13/004 , G11C7/04 , G11C13/0004 , G11C13/0069 , G11C2013/0054 , G11C2013/0092 , G11C2213/79
摘要： At the time of, for example, a set operation (SET) for making a phase-change element in a crystalline state, a pulse of a voltage Vreset required for melting the element is applied to the phase-change element, and subsequently a pulse of a voltage Vset that is lower than Vreset and is required for crystallizing the element is applied thereto. And, the magnitude of this voltage Vset is then changed depending on the ambient temperature so that the magnitude of the voltage Vset is small as the temperature becomes high (TH). In this manner, a margin of a write operation between the set operation and a reset operation (RESET) for making the element to be in amorphous state is improved.
摘要翻译： 在例如用于使相变元件处于结晶状态的设定操作（SET）时，将元件熔化所需的电压Vreset的脉冲施加到相变元件，随后将脉冲 的电压Vset低于Vreset，并且是将元件结晶所需要的。 而且，该电压Vset的大小然后根据环境温度而改变，使得随着温度变高（TH），电压Vset的大小较小。 以这种方式，提高了设置操作和用于使元件处于非晶态的复位操作（RESET）之间的写入操作余量。
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公开(公告)号：US08031511B2
公开(公告)日：2011-10-04
申请号：US13024252
申请日：2011-02-09
CPC分类号： G11C13/004 , G11C7/04 , G11C13/0004 , G11C13/0069 , G11C2013/0054 , G11C2013/0092 , G11C2213/79
摘要： At the time of, for example, a set operation (SET) for making a phase-change element in a crystalline state, a pulse of a voltage Vreset required for melting the element is applied to the phase-change element, and subsequently a pulse of a voltage Vset that is lower than Vreset and is required for crystallizing the element is applied thereto. And, the magnitude of this voltage Vset is then changed depending on the ambient temperature so that the magnitude of the voltage Vset is small as the temperature becomes high (TH). In this manner, a margin of a write operation between the set operation and a reset operation (RESET) for making the element to be in amorphous state is improved.
摘要翻译： 在例如用于使相变元件处于结晶状态的设定操作（SET）时，将元件熔化所需的电压Vreset的脉冲施加到相变元件，随后将脉冲 的电压Vset低于Vreset，并且是将元件结晶所需要的。 而且，该电压Vset的大小然后根据环境温度而改变，使得随着温度变高（TH），电压Vset的大小较小。 以这种方式，提高了设置操作和用于使元件处于非晶态的复位操作（RESET）之间的写入操作余量。
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公开(公告)号：US06977858B2
公开(公告)日：2005-12-20
申请号：US10728965
申请日：2003-12-08
IPC分类号： G11C11/413 , G06F11/10 , G11C7/22 , G11C7/24 , G11C29/00 , G11C29/42 , H01L21/8244 , H01L27/10 , H01L27/11 , G11C7/00
CPC分类号： G06F11/1008 , G06F11/108 , G11C5/025 , G11C7/22 , G11C7/24 , G11C8/20 , G11C11/412 , G11C2207/2218 , G11C2207/229 , H01L27/0207 , H01L27/1104
摘要： A semiconductor device comprises, a plurality of memory cells, and an error-correction circuit, wherein write operation is performed by a late-write method, and ECC processing is executed in parallel with writing, and thereby cycle time is shortened. Moreover, it is better that when a memory cell is power supplied through a well tap, the same address is not assigned while the memory cell is power supplied through the well tap.
摘要翻译： 半导体器件包括多个存储器单元和纠错电路，其中通过后置写入方法进行写入操作，并且与写入并行执行ECC处理，从而缩短了周期时间。 此外，当存储单元通过阱抽头供电时，更好的是，当存储单元通过井口供电时，不分配相同的地址。
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6.发明授权Semiconductor memory device layout comprising high impurity well tap areas for supplying well voltages to N wells and P wells 失效半导体存储器件布局包括用于向N个井和P井提供井电压的高杂质阱抽头区域公开(公告)号：US07692943B2
公开(公告)日：2010-04-06
申请号：US12000135
申请日：2007-12-10
IPC分类号： G11C5/02
CPC分类号： G06F11/1008 , G06F11/108 , G11C5/025 , G11C7/22 , G11C7/24 , G11C8/20 , G11C11/412 , G11C2207/2218 , G11C2207/229 , H01L27/0207 , H01L27/1104
摘要： A semiconductor device includes a plurality of memory cells, and an error-correction circuit. Its write operation is performed by a late-write method, and ECC processing is executed in parallel with writing to shorten a cycle time. Moreover, when a memory cell is power-supplied through a well tap, the same address is not assigned while the memory cell is power-supplied through the well tap.
摘要翻译： 半导体器件包括多个存储单元和纠错电路。 其写入操作是通过后期写入方式进行的，并且与写入并行执行ECC处理以缩短周期时间。 此外，当存储单元通过阱抽头供电时，在存储单元通过井口供电时，不分配相同的地址。
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公开(公告)号：US20060028853A1
公开(公告)日：2006-02-09
申请号：US11242054
申请日：2005-10-04
CPC分类号： G06F11/1008 , G06F11/108 , G11C5/025 , G11C7/22 , G11C7/24 , G11C8/20 , G11C11/412 , G11C2207/2218 , G11C2207/229 , H01L27/0207 , H01L27/1104
摘要： According to one aspect of the present invention, there is provided a semiconductor device comprising a plurality of memory cells, and an error-correction circuit, wherein write operation is performed by a late-write method, and ECC processing is executed in parallel with writing, and thereby cycle time is shortened. Moreover, it is better that when a memory cell is power supplied through a well tap, the same address is not assigned while the memory cell is power supplied through the well tap.
摘要翻译： 根据本发明的一个方面，提供了一种包括多个存储单元的半导体器件和一个纠错电路，其中写操作是通过后期写入方式执行的，ECC处理与写入并行执行 ，从而缩短周期时间。 此外，当存储单元通过阱抽头供电时，更好的是，当存储单元通过井口供电时，不分配相同的地址。
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8.发明授权Semiconductor memory device layout comprising high impurity well tap areas for supplying well voltages to N wells and P wells 有权半导体存储器件布局包括用于向N个井和P井提供井电压的高杂质阱抽头区域公开(公告)号：US07319603B2
公开(公告)日：2008-01-15
申请号：US11242054
申请日：2005-10-04
IPC分类号： G11C5/02
CPC分类号： G06F11/1008 , G06F11/108 , G11C5/025 , G11C7/22 , G11C7/24 , G11C8/20 , G11C11/412 , G11C2207/2218 , G11C2207/229 , H01L27/0207 , H01L27/1104
摘要： A semiconductor device includes a plurality of memory cells, and an error-correction circuit. Its write operation is performed by a late-write method, and ECC processing is executed in parallel with writing to shorten a cycle time. Moreover, when a memory cell is power-supplied through a well tap, the same address is not assigned while the memory cell is power-supplied through the well tap.
摘要翻译： 半导体器件包括多个存储单元和纠错电路。 其写入操作是通过后期写入方式进行的，并且与写入并行执行ECC处理以缩短周期时间。 此外，当存储单元通过阱抽头供电时，在存储单元通过井口供电时，不分配相同的地址。
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公开(公告)号：US07388238B2
公开(公告)日：2008-06-17
申请号：US11452275
申请日：2006-06-14
申请人： Kenichi Osada , Koichiro Ishibashi , Yoshikazu Saitoh , Akio Nishida , Masaru Nakamichi , Naoki Kitai
发明人： Kenichi Osada , Koichiro Ishibashi , Yoshikazu Saitoh , Akio Nishida , Masaru Nakamichi , Naoki Kitai
IPC分类号： H01L27/10
CPC分类号： G11C11/412 , G11C11/40 , G11C11/413 , G11C11/418 , H01L21/823475 , H01L21/823493 , H01L21/823814 , H01L21/82385 , H01L27/088 , H01L27/092 , H01L27/105 , H01L27/1052 , H01L27/11 , H01L27/1104 , H01L27/1116 , H03K19/0016
摘要： The gate tunnel leakage current is increased in the up-to-date process, so that it is necessary to reduce the gate tunnel leakage current in the LSI which is driven by a battery for use in a cellular phone and which needs to be in a standby mode at a low leakage current. In a semiconductor integrated circuit device, the ground source electrode lines of logic and memory circuits are kept at a ground potential in an active mode, and are kept at a voltage higher than the ground potential in an unselected standby mode. The gate tunnel leakage current can be reduced without destroying data.
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公开(公告)号：US07569881B2
公开(公告)日：2009-08-04
申请号：US12078992
申请日：2008-04-09
申请人： Kenichi Osada , Koichiro Ishibashi , Yoshikazu Saitoh , Akio Nishida , Masaru Nakamichi , Naoki Kitai
发明人： Kenichi Osada , Koichiro Ishibashi , Yoshikazu Saitoh , Akio Nishida , Masaru Nakamichi , Naoki Kitai
IPC分类号： H01L29/788 , H01L21/8242
CPC分类号： G11C11/412 , G11C11/40 , G11C11/413 , G11C11/418 , H01L21/823475 , H01L21/823493 , H01L21/823814 , H01L21/82385 , H01L27/088 , H01L27/092 , H01L27/105 , H01L27/1052 , H01L27/11 , H01L27/1104 , H01L27/1116 , H03K19/0016
摘要： The gate tunnel leakage current is increased in the up-to-date process, so that it is necessary to reduce the gate tunnel leakage current in the LSI which is driven by a battery for use in a cellular phone and which needs to be in a standby mode at a low leakage current. In a semiconductor integrated circuit device, the ground source electrode lines of logic and memory circuits are kept at a ground potential in an active mode, and are kept at a voltage higher than the ground potential in an unselected standby mode. The gate tunnel leakage current can be reduced without destroying data.
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