Systems and Methods for Codec Usage Control During Storage Pre-read
    91.
    发明申请
    Systems and Methods for Codec Usage Control During Storage Pre-read 有权
    存储预读期间编码器使用控制的系统和方法

    公开(公告)号:US20100322048A1

    公开(公告)日:2010-12-23

    申请号:US12487638

    申请日:2009-06-18

    IPC分类号: G11B20/00

    摘要: Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing circuit is disclosed that includes an increased iteration enable signal, a first detector circuit, a second detector circuit, and a data decoding circuit. The first detector circuit receives a data set and performs a data detection on the data set to provide a detected data set. The data decoding circuit receives a derivative of the detected data set and performs a decoding process to provide a decoded data set. The decoded data set is provided to the second detector circuit based at least in part on an assertion level of the increased iteration enable signal.

    摘要翻译: 本发明的各种实施例提供了用于数据处理的系统和方法。 例如,公开了一种数据处理电路,其包括增加的迭代使能信号,第一检测器电路,第二检测器电路和数据解码电路。 第一检测器电路接收数据组并对数据集执行数据检测以提供检测数据集。 数据解码电路接收检测数据组的导数,并进行解码处理,提供解码数据组。 解码数据集至少部分地基于增加的迭代使能信号的断言电平被提供给第二检测器电路。

    Power Reduced Queue Based Data Detection and Decoding Systems and Methods for Using Such
    92.
    发明申请
    Power Reduced Queue Based Data Detection and Decoding Systems and Methods for Using Such 有权
    基于功率减少的队列数据检测和解码系统及其使用方法

    公开(公告)号:US20100070837A1

    公开(公告)日:2010-03-18

    申请号:US12270713

    申请日:2008-11-13

    IPC分类号: H04L1/00

    摘要: Various embodiments of the present invention provide systems and methods for data processing. For example, a variable iteration data processing system is disclosed that includes a first detector, a second detector, a decoder and a unified memory buffer. An input data set is received by the first detector that performs a data detection and provides a first detected data set. The decoder receives a derivative of the first detected data set and performs a decoding operation that yields a decoded data set. In some cases, the derivative of the first detected data set is an interleaved version of the first detected data set. The decoded data set is written to a unified memory buffer. The first decoded data set is retrievable from the unified memory buffer and a derivative thereof is provided to the second detector. In some cases, the derivative of the decoded is a de-interleaved version of the decoded data set. The second detector is operable to perform a data detection on the derivative of the decoded data set and to provide a second detected data set that is written to the unified memory buffer.

    摘要翻译: 本发明的各种实施例提供了用于数据处理的系统和方法。 例如,公开了包括第一检测器,第二检测器,解码器和统一存储器缓冲器的可变迭代数据处理系统。 由执行数据检测的第一检测器接收输入数据集,并提供第一检测数据集。 解码器接收第一检测数据集的导数,并执行产生解码数据集的解码操作。 在一些情况下,第一检测数据集的导数是第一检测数据集的交错版本。 解码的数据集被写入统一的存储缓冲器。 第一解码数据集可从统一存储器缓冲器检索,并且其导数被提供给第二检测器。 在一些情况下,解码的导数是解码数据集的解交织版本。 第二检测器可操作以对解码数据集的导数执行数据检测,并提供写入统一存储器缓冲器的第二检测数据集。

    ERROR-CORRECTION DECODER EMPLOYING CHECK-NODE MESSAGE AVERAGING
    93.
    发明申请
    ERROR-CORRECTION DECODER EMPLOYING CHECK-NODE MESSAGE AVERAGING 有权
    错误修正解码器使用检查节点消息平均

    公开(公告)号:US20100042891A1

    公开(公告)日:2010-02-18

    申请号:US12475786

    申请日:2009-06-01

    IPC分类号: H03M13/05 G06F11/10

    摘要: In one embodiment, an LDPC decoder has a controller and one or more check-node units (CNUs). Each CNU is selectively configurable to operate in (i) a first mode that updates check-node (i.e., R) messages without averaging and (ii) a second mode that that updates R messages using averaging. Initially, each CNU is configured in the first mode to generate non-averaged R messages, and the decoder attempts to recover an LDPC-encoded codeword using the non-averaged R messages. If the decoder is unable to recover the correct codeword, then (i) the controller selects the averaging mode, (ii) each CNU is configured to operate in the second mode to generate averaged R messages, and (iii) the decoder attempts to recover the correct codeword using the averaged R messages. Averaging the R messages may slow down the propagation of erroneous messages that lead the decoder to convergence on trapping sets.

    摘要翻译: 在一个实施例中,LDPC解码器具有控制器和一个或多个校验节点单元(CNU)。 每个CNU可选择性地配置为在(i)不平均更新校验节点(即,R)消息的第一模式和(ii)使用平均来更新R消息的第二模式。 最初,每个CNU被配置为第一模式以产生非平均的R消息,并且解码器尝试使用非平均的R消息来恢复LDPC编码的码字。 如果解码器不能恢复正确的码字,则(i)控制器选择平均模式,(ii)每个CNU被配置为在第二模式下操作以产生平均的R消息,并且(iii)解码器尝试恢复 使用平均R消息的正确码字。 平均R消息可能会减慢导致解码器收敛的错误消息的传播。

    Systems and methods for monitoring out of order data decoding
    94.
    发明授权
    Systems and methods for monitoring out of order data decoding 有权
    用于监视无序数据解码的系统和方法

    公开(公告)号:US08688873B2

    公开(公告)日:2014-04-01

    申请号:US12651254

    申请日:2009-12-31

    IPC分类号: G06F3/00 G06F5/00

    摘要: Various embodiments of the present invention provide systems and methods for monitoring out of order data decoding. For example, a method for monitoring out of order data processing is provided that includes receiving a plurality of data sets that is associated with a plurality of identifiers with each of the plurality of identifiers indicates a respective one of the plurality of data sets; storing each of the plurality of identifiers in a FIFO memory in an order that the corresponding data sets of the plurality of data sets was received; processing the plurality of data sets such that at least one of the plurality of data sets is provided as an output data set; accessing the next available identifier from the FIFO memory; and asserting an out of order signal when the next available identifier is not the same as the identifier associated with the output data set.

    摘要翻译: 本发明的各种实施例提供用于监视异步数据解码的系统和方法。 例如,提供了一种用于监视不合格数据处理的方法,包括接收与多个标识符相关联的多个数据集,所述多个标识符中的每一个标识符指示所述多个数据集中的相应一个; 将多个标识符中的每一个按照接收到多个数据集的相应数据集的顺序存储在FIFO存储器中; 处理所述多个数据集,使得所述多个数据集中的至少一个被提供为输出数据集; 从FIFO存储器访问下一个可用标识符; 并且当下一个可用标识符与与输出数据集相关联的标识符不相同时,断言无序信号。

    Systems and methods for updating detector parameters in a data processing circuit
    95.
    发明授权
    Systems and methods for updating detector parameters in a data processing circuit 有权
    用于更新数据处理电路中检测器参数的系统和方法

    公开(公告)号:US08578253B2

    公开(公告)日:2013-11-05

    申请号:US12651956

    申请日:2010-01-04

    IPC分类号: H03M13/00

    摘要: Various embodiments of the present invention provide systems and methods for updating detector parameters in a data processing circuit. For example, a data processing circuit is disclosed that includes a first detector circuit, a second detector circuit, and a calibration circuit. The first detector circuit is operable to receive a first data set and to apply a data detection algorithm to the first data set, and the second detector circuit is operable to receive a second data set and to apply the data detection algorithm to the second data set. The calibration circuit is operable to calculate a data detection parameter based upon a third data set. The data detection parameter is used by the first detector circuit in applying the data detection algorithm to the first data set during a period that the data detection parameter is used by the second detector circuit in applying the data detection algorithm to the second data set.

    摘要翻译: 本发明的各种实施例提供用于在数据处理电路中更新检测器参数的系统和方法。 例如,公开了一种包括第一检测器电路,第二检测器电路和校准电路的数据处理电路。 第一检测器电路可操作以接收第一数据集并将数据检测算法应用于第一数据集,并且第二检测器电路可操作以接收第二数据集并将数据检测算法应用于第二数据集 。 校准电路可操作以基于第三数据集计算数据检测参数。 数据检测参数由第一检测器电路在将数据检测算法应用于第二数据集时由第二检测器电路使用的时段期间将数据检测算法应用于第一数据集使用。

    Systems and methods for codec usage control during storage pre-read
    96.
    发明授权
    Systems and methods for codec usage control during storage pre-read 有权
    存储预读过程中编解码器使用控制的系统和方法

    公开(公告)号:US08250434B2

    公开(公告)日:2012-08-21

    申请号:US12487638

    申请日:2009-06-18

    IPC分类号: H03M13/00

    摘要: Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing circuit is disclosed that includes an increased iteration enable signal, a first detector circuit, a second detector circuit, and a data decoding circuit. The first detector circuit receives a data set and performs a data detection on the data set to provide a detected data set. The data decoding circuit receives a derivative of the detected data set and performs a decoding process to provide a decoded data set. The decoded data set is provided to the second detector circuit based at least in part on an assertion level of the increased iteration enable signal.

    摘要翻译: 本发明的各种实施例提供了用于数据处理的系统和方法。 例如,公开了一种数据处理电路,其包括增加的迭代使能信号,第一检测器电路,第二检测器电路和数据解码电路。 第一检测器电路接收数据组并对数据集执行数据检测以提供检测数据集。 数据解码电路接收检测数据组的导数,并进行解码处理,提供解码数据组。 解码数据集至少部分地基于增加的迭代使能信号的断言电平被提供给第二检测器电路。

    Programmable quasi-cyclic low-density parity check (QC LDPC) encoder for read channel
    97.
    发明申请
    Programmable quasi-cyclic low-density parity check (QC LDPC) encoder for read channel 有权
    用于读通道的可编程准循环低密度奇偶校验(QC LDPC)编码器

    公开(公告)号:US20100100788A1

    公开(公告)日:2010-04-22

    申请号:US12288221

    申请日:2008-10-17

    IPC分类号: H03M13/27 G06F11/10

    摘要: The present invention is a programmable QC LDPC encoder for encoding user data. The encoder may be configurable for implementation with a read channel. The encoder may include a plurality of barrel shifter circuits. The barrel shifter circuits are configured for generating a plurality of parity bits based on interleaved user bits received by the encoder. The barrel shifter circuits are further configured for outputting the parity bits. The encoder may further include an encoder interleaver memory. The encoder interleaver memory may be communicatively coupled with the barrel shifter circuits and may receive the parity bits output from the barrel shifter circuits. The encoder interleaver may be configured for interleaving the parity bits. Further, the encoder may be configured for outputting the interleaved parity bits to a multiplexer. The barrel shifter circuits may generate the plurality of parity bits via an encoding algorithm: p=u*GT.

    摘要翻译: 本发明是用于编码用户数据的可编程QC LDPC编码器。 编码器可以被配置为用读通道实现。 编码器可以包括多个桶形移位器电路。 桶形移位器电路被配置为基于由编码器接收的交织的用户比特生成多个奇偶校验位。 桶形移位器电路还被配置为输出奇偶校验位。 编码器还可以包括编码器交织器存储器。 编码器交织器存储器可以与桶形移位器电路通信耦合,并且可以接收从桶形移位器电路输出的奇偶校验位。 编码器交织器可以被配置为交织奇偶校验位。 此外,编码器可以被配置为将交错的奇偶校验位输出到多路复用器。 桶形移位器电路可以通过编码算法生成多个奇偶校验位:p = u * GT。

    ADJUSTING INPUT SAMPLES IN TURBO EQUALIZATION SCHEMES TO BREAK TRAPPING SETS
    98.
    发明申请
    ADJUSTING INPUT SAMPLES IN TURBO EQUALIZATION SCHEMES TO BREAK TRAPPING SETS 有权
    在涡轮均衡方案中调整输入样本以打破陷阱

    公开(公告)号:US20100042905A1

    公开(公告)日:2010-02-18

    申请号:US12540035

    申请日:2009-08-12

    IPC分类号: H03M13/45 H03M13/05 H03M13/37

    摘要: In one embodiment, a turbo equalizer has a channel detector that receives equalized samples and generates channel soft-output values. An LDPC decoder attempts to decode the channel soft-output values to recover an LDPC-encoded codeword. If the decoder converges on a trapping set, then an adjustment block selects one or more of the equalized samples based on one or more specified conditions and adjusts the selected equalized samples. Selection may be performed by identifying the locations of unsatisfied check nodes of the last local decoder iteration and selecting the equalized samples that correspond to bit nodes of the LDPC-encoded codeword that are connected to the unsatisfied check nodes. Adjustment of the equalized samples may be performed using any combination of scaling, offsetting, and saturation. Channel detection is then performed using the adjusted equalized samples to generate an updated set of channel soft-output values, which are subsequently decoded by the decoder.

    摘要翻译: 在一个实施例中,turbo均衡器具有信道检测器,其接收均衡的样本并产生信道软输出值。 LDPC解码器尝试对通道软输出值进行解码以恢复LDPC编码的码字。 如果解码器收敛于捕获集合,则调整块基于一个或多个指定条件选择一个或多个均衡样本,并调整所选择的均衡样本。 可以通过识别最后的本地解码器迭代的不满足的校验节点的位置并选择与连接到不满足的校验节点的LDPC编码码字的比特节点相对应的均衡样本来执行选择。 可以使用缩放,偏移和饱和度的任何组合来执行均衡样本的调整。 然后使用经调整的均衡采样来执行信道检测,以产生随后由解码器解码的更新的信道软输出值集合。

    Systems and methods for sample averaging in data processing
    100.
    发明授权
    Systems and methods for sample averaging in data processing 有权
    数据处理中采样平均的系统和方法

    公开(公告)号:US08693120B2

    公开(公告)日:2014-04-08

    申请号:US13050765

    申请日:2011-03-17

    IPC分类号: G11B5/09

    摘要: Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit is disclosed that includes a read circuit and a combining circuit. The read circuit is operable to provide a first instance of a user data set, a second instance of the user data set, and a third instance of the user data set. The combining circuit is operable to: combine at least a first segment of the first instance of the user data set with a first segment of the second instance of the user data set to yield a first combined data segment; provide a second combined data set that includes a combination of one or more second segments from the second instance of the user data set and the third instance of the user data set; and provide an aggregate data set including at least the first combined data set and the second combined data set. The second combined data set does not incorporate a second segment of the first instance of the user data set.

    摘要翻译: 本发明的各种实施例提供了用于数据处理的系统和方法。 作为示例,公开了包括读取电路和组合电路的数据处理电路。 读取电路可操作以提供用户数据集的第一实例,用户数据集的第二实例以及用户数据集的第三实例。 组合电路可操作为:将用户数据集的第一实例的至少第一段与用户数据集的第二实例的第一段组合以产生第一组合数据段; 提供第二组合数据集,其包括来自用户数据集的第二实例和用户数据集的第三实例的一个或多个第二段的组合; 并提供包括至少第一组合数据集和第二组合数据集的聚合数据集。 第二组合数据集不包括用户数据集的第一实例的第二段。