公开(公告)号：US07117332B2

公开(公告)日：2006-10-03

申请号：US10632195

申请日：2003-07-31

Applicant: Chun-Hung Lin ,  Chih-Hung Wang ,  Chun-Hao Kuo

Inventor： Chun-Hung Lin ,  Chih-Hung Wang ,  Chun-Hao Kuo

IPC: G06F12/00

CPC classification number: G06F12/0246 ,  G06F11/1068 ,  G06F11/1435 ,  G06F12/0292 ,  G06F2212/7203

Abstract: A window-based flash memory storage system and a management and an access method therefor are proposed. The window-based flash memory storage system includes a window-based region and a redundant reserved region; wherein the window-based region is used to store a number of windows, each window being associated with a number of physical blocks. The redundant reserved region includes a dynamic-link area, a window-information area, a dynamic-link information area, and an boot-information area; wherein the dynamic-link area includes a plurality of dynamic allocation blocks, each being allocatable to any window. The window-information area is used to store a specific window-information set that is dedicated to a certain window within a specific range of data storage space. The dynamic-link information area is used to record the status of the allocation of the dynamic allocation blocks to the windows.

公开(公告)号：US07094649B2

公开(公告)日：2006-08-22

申请号：US10886981

申请日：2004-07-07

Applicant: Chien-Hsing Lee ,  Chin-Hsi Lin ,  Jhyy-Cheng Liou

Inventor： Chien-Hsing Lee ,  Chin-Hsi Lin ,  Jhyy-Cheng Liou

IPC: H01L21/8236

CPC classification number: G11C11/5692 ,  G11C16/0483 ,  H01L27/112 ,  H01L27/1122 ,  H01L27/1126

Abstract: The present invention relates to a multi-level read only memory cell that can store two bits and the fabrication method thereof. The multi-level ROM cell has the storage capacity of two bits and the resultant NAND type ROM memory array can provide four logic states of two bits, thus increasing the data storage capacity.

Abstract translation: 本发明涉及可存储两位的多级只读存储器单元及其制造方法。 多级ROM单元具有两位的存储容量，并且所得的NAND型ROM存储器阵列可以提供两位的四个逻辑状态，从而增加数据存储容量。

公开(公告)号：US07058784B2

公开(公告)日：2006-06-06

申请号：US10604247

申请日：2003-07-04

Applicant: Chih-Hung Wang

Inventor： Chih-Hung Wang

IPC: G06F12/02

CPC classification number: G06F12/0246 ,  G06F2212/2022 ,  G06F2212/7202 ,  G06F2212/7203

Abstract: A method for managing the access procedure for large block flash memory by employing a page cache block, so as to reduce the occurrence of swap operation is proposed. At least one block of the nonvolatile memory is used as a page cache block. When a host requests to write a data to storage device, the last page of the data is written into one available page of the page cache block by the controller. A block structure is defined in the controller having a data block for storing original data, a writing block for temporary data storage in the access operation, and a page cache block for storing the last one page data to be written.

Abstract translation: 提出了一种通过采用页面缓存块来管理大块闪存的访问过程的方法，以便减少交换操作的发生。 非易失性存储器的至少一个块被用作页面高速缓存块。 当主机请求将数据写入存储设备时，数据的最后一页由控制器写入页面缓存块的一个可用页面。 在具有用于存储原始数据的数据块，用于访问操作中的临时数据存储的写入块和用于存储要写入的最后一页数据的页面高速缓存块的控制器中定义了块结构。

公开(公告)号：US07046549B2

公开(公告)日：2006-05-16

申请号：US10707665

申请日：2003-12-31

Applicant: Chien-Hsing Lee ,  Chin-Hsi Lin ,  Jhyy-Cheng Liou

Inventor： Chien-Hsing Lee ,  Chin-Hsi Lin ,  Jhyy-Cheng Liou

IPC: G11C16/04

CPC classification number: G11C16/3468

Abstract: The invention is directed to a layout of nonvolatile memory device. The memory cell has a gate electrode, a first doped electrode, and a second doped electrode. The first doped electrode is coupled to the bit line. The gate electrode is coupled to one separated word line. A shared coupled capacitor structure is coupled between all of memory cells of the adjacent bit lines from the second doped electrode. The capacitor structure has at least two floating-gate MOS capacitors. Each floating-gate MOS capacitor has a floating-gate transistor having a floating gate, a first S/D region and a second S/D region; and a MOS capacitor coupled to the floating gate. The first S/D region is coupled to the second doped electrode of the corresponding one of the transistor memory cells, and the second S/D region is shared with an adjacent one of the floating-gate transistor.

Abstract translation: 本发明涉及非易失性存储器件的布局。 存储单元具有栅电极，第一掺杂电极和第二掺杂电极。 第一掺杂电极耦合到位线。 栅电极耦合到一个分离的字线。 共享耦合电容器结构耦合在来自第二掺杂电极的相邻位线的所有存储单元之间。 电容器结构具有至少两个浮栅MOS电容器。 每个浮栅MOS电容器具有浮置晶体管，其具有浮置栅极，第一S / D区域和第二S / D区域; 以及耦合到浮动栅极的MOS电容器。 第一S / D区域耦合到相应一个晶体管存储单元的第二掺杂电极，并且第二S / D区域与浮置栅晶体管的相邻一个共享。

公开(公告)号：US07020018B2

公开(公告)日：2006-03-28

申请号：US10987045

申请日：2004-11-12

Applicant: Tsung-Min Hsieh ,  Jhyy-Cheng Liou ,  Chien-Hsing Lee ,  Chin-Hsi Lin

Inventor： Tsung-Min Hsieh ,  Jhyy-Cheng Liou ,  Chien-Hsing Lee ,  Chin-Hsi Lin

IPC: G11C16/04

CPC classification number: G11C16/0491 ,  G11C16/0475 ,  H01L27/115 ,  H01L27/11568

Abstract: A structure of non-volatile memory has a plurality of buried bit lines in a substrate, extending along a first direction. Selection gate structure lines are located between the buried bit lines. A plurality of stack dielectric films on the both sides of the selection gate structure lines serving as a charge storage region, does not extend to the bit lines and a dielectric layer contacting a surface of substrate adjacent to stacked dielectric films. Word lines are over the substrate, wherein stacked dielectric films and a dielectric layer are interposed between WL and substrate on the region excluding the selection gate structure line, extending along a second direction different from the first direction. Since the charge storage layer does not completely cover between the selection gate structure lines and the bit lines, an additional control gate is formed.

Abstract translation: 非易失性存储器的结构在衬底中具有沿着第一方向延伸的多个掩埋位线。 选择栅极结构线位于掩埋位线之间。 在用作电荷存储区域的选择栅极结构线的两侧上的多个堆叠电介质膜不延伸到位线，并且电介质层与基板的与堆叠的电介质膜相邻的表面接触。 字线在衬底上方，其中堆叠的电介质膜和电介质层插入在除了选择栅极结构线之外的区域之间的WL和衬底之间，沿着不同于第一方向的第二方向延伸。 由于电荷存储层不完全覆盖在选择栅极结构线和位线之间，所以形成附加的控制栅极。

公开(公告)号：US07015553B2

公开(公告)日：2006-03-21

申请号：US10478017

申请日：2002-08-26

Applicant: Jhyy-Cheng Liou ,  Chin-Hsi Lin

Inventor： Jhyy-Cheng Liou ,  Chin-Hsi Lin

IPC: H01L29/76 ,  G11C17/00

CPC classification number: H01L27/11233 ,  G11C17/12 ,  H01L27/105 ,  H01L27/112 ,  H01L27/11226 ,  H01L27/1126 ,  H01L27/11293

Abstract: A compact mask programmable read-only memory (Mask ROM) is described, comprising a plurality of word lines, a plurality of bit lines, and a plurality of MOS-type and diffusion-type memory cells arranged in an array. The memory cells in one column are coupled to one bit line, and the gates of the MOS-type cells in one row are coupled to one word line via contacts, wherein two columns of memory cells share a column of contacts. A MOS-type cell shares its source and drain with two memory cells in the same column, and a diffusion-type cell directly connects with the diffusions of two adjacent memory cells. A constant number of continuous memory cells are grouped as a memory string, wherein the two diffusions of the two terminal memory cells are electrically connected to a bank select transistor and a ground line, respectively.

Abstract translation: 描述了紧凑的掩模可编程只读存储器（掩模ROM），其包括多个字线，多个位线以及排列成阵列的多个MOS型和扩散型存储单元。 一列中的存储单元耦合到一个位线，并且一行中的MOS型单元的栅极经由触点耦合到一个字线，其中两列存储器单元共享一列触点。 MOS型电池与同一列中的两个存储单元共用其源极和漏极，扩散型单元与两个相邻存储单元的扩散直接连接。 恒定数量的连续存储器单元被分组为存储器串，其中两个端子存储单元的两个扩散分别电连接到存储体选择晶体管和接地线。