公开(公告)号：US07696557B2

公开(公告)日：2010-04-13

申请号：US11706587

申请日：2007-02-15

申请人： Chun Chen ,  Andrei Mihnea ,  Kirk Prall

发明人： Chun Chen ,  Andrei Mihnea ,  Kirk Prall

IPC分类号： H01L29/788

CPC分类号： H01L27/11519 ,  H01L27/115 ,  H01L27/11521

摘要： Floating-gate field-effect transistors or memory cells formed in isolated wells are useful in the fabrication of non-volatile memory arrays and devices. A column of such floating-gate memory cells are associated with a well containing the source/drain regions for each memory cell in the column. These wells are isolated from source/drain regions of other columns of the array. Fowler-Nordheim tunneling can be used to program and erase such floating-gate memory cells either on an individual basis or on a bulk or block basis.

摘要翻译： 在隔离阱中形成的浮栅场效应晶体管或存储单元在制造非易失性存储器阵列和器件中是有用的。 这种浮栅存储器单元的列与包含列中的每个存储器单元的源极/漏极区的阱相关联。 这些阱与阵列的其他列的源/漏区隔离。 可以使用Fowler-Nordheim隧道来编程和擦除这种浮动栅极存储器单元，无论是单独的还是以块或块为基础的。

公开(公告)号：US07499325B2

公开(公告)日：2009-03-03

申请号：US11614820

申请日：2006-12-21

申请人： Daniel H. Doyle ,  Mark Helm ,  Andrei Mihnea

发明人： Daniel H. Doyle ,  Mark Helm ,  Andrei Mihnea

IPC分类号： G11C16/04

CPC分类号： G11C16/0483 ,  G11C16/16

摘要： Some embodiments include a device having memory cells coupled to a well of a semiconductor substrate, and a select transistor coupled between the memory cells and a bit line of the device. The device may have a first circuit to raise a well voltage of the well from a first well voltage level to a second well voltage level during an erase operation. The first circuit may hold the well at the second well voltage level for a time interval during the erase operation. The device may have a second circuit to raise a voltage of the gate of the select transistor from a first gate voltage level to a second gate voltage level, which may be lower than the second well voltage level. The second circuit may hold the gate at the second gate voltage level for a time interval during the erase operation. Other embodiments including additional apparatus, systems, and methods are disclosed.

摘要翻译： 一些实施例包括具有耦合到半导体衬底的阱的存储器单元的器件和耦合在存储器单元和器件的位线之间的选择晶体管。 器件可以具有第一电路，以在擦除操作期间将阱的阱电压从第一阱电压电平升高到第二阱电压电平。 在擦除操作期间，第一电路可以将阱保持在第二阱电压电平一段时间间隔。 器件可以具有第二电路，以将选择晶体管的栅极的电压从第一栅极电压电平升高到可能低于第二阱电压电平的第二栅极电压电平。 第二电路可以在擦除操作期间将栅极保持在第二栅极电压电平一段时间间隔。 公开了包括附加装置，系统和方法的其它实施例。

公开(公告)号：US20090003078A1

公开(公告)日：2009-01-01

申请号：US11821914

申请日：2007-06-26

申请人： Andrei Mihnea ,  Todd Marquart ,  Jeffrey Kessenich

发明人： Andrei Mihnea ,  Todd Marquart ,  Jeffrey Kessenich

IPC分类号： G11C11/34

CPC分类号： G11C8/12 ,  G11C8/08 ,  G11C16/0483 ,  G11C16/3454 ,  G11C16/3459

摘要： Methods and devices are disclosed, such methods comprising applying a verify pass-through voltage to unselected select lines of the floating-gate memory array that is greater than a read pass-through voltage applied to the unselected select lines. Other methods involve utilizing a cell current for reading a value from one or more memory cells in program-verify operations that is lower than a cell current for reading value from one or more memory cells in read operations.

摘要翻译： 公开了方法和装置，这样的方法包括将验证直通电压施加到浮选存储器阵列的未选择的选择线，该选择线大于施加到未选择的选择线的读通过电压。 其他方法涉及利用单元电流来读取来自读取操作中的一个或多个存储器单元的值的单元电流低于程序验证操作中的一个或多个存储器单元的值。

公开(公告)号：US20080298123A1

公开(公告)日：2008-12-04

申请号：US11809180

申请日：2007-05-31

申请人： Andrei Mihnea ,  William Kueber ,  Mark Helm

发明人： Andrei Mihnea ,  William Kueber ,  Mark Helm

IPC分类号： G11C11/34

CPC分类号： G11C16/3404 ,  G11C16/0483

摘要： Embodiments of the present disclosure provide methods, devices, modules, and systems for healing non-volatile memory cells. One method includes biasing a first select gate transistor coupled to a string of memory cells at a first voltage, biasing a second select gate transistor coupled to the string at a second voltage, applying a first healing voltage to a first edge word line in order to extract charge accumulated between the first select gate transistor and a first edge memory cell stack of the string, and applying a second healing voltage to a second edge word line in order to extract charge accumulated between the second select gate transistor and a second edge memory cell stack of the string.

摘要翻译： 本公开的实施例提供了用于治疗非易失性存储器单元的方法，装置，模块和系统。 一种方法包括以第一电压偏置耦合到一串存储器单元的第一选择栅极晶体管，以第二电压偏置耦合到串的第二选择栅极晶体管，将第一愈合电压施加到第一边缘字线，以便 提取在第一选择栅极晶体管和串的第一边缘存储单元堆之间累积的电荷，以及向第二边缘字线施加第二愈合电压，以便提取在第二选择栅极晶体管和第二边缘存储单元之间累积的电荷 堆栈的字符串。

公开(公告)号：US07280395B2

公开(公告)日：2007-10-09

申请号：US11217952

申请日：2005-09-01

申请人： Andrei Mihnea ,  Chun Chen

发明人： Andrei Mihnea ,  Chun Chen

IPC分类号： G11C11/34

CPC分类号： G11C16/16 ,  G11C16/08 ,  G11C16/14 ,  H01L27/115

摘要： Methods for neutralizing holes in tunnel oxides of floating-gate memory cells and devices using a decrease in magnitude of a source voltage of a first polarity to increase the magnitude of a control gate voltage of a second polarity.

摘要翻译： 使用第一极性的源极电压的幅度的减小来中和浮栅存储器单元的隧道氧化物中的空穴的方法，以增加第二极性的控制栅极电压的幅度。

公开(公告)号：US07272045B2

公开(公告)日：2007-09-18

申请号：US11339399

申请日：2006-01-25

申请人： Andrei Mihnea

发明人： Andrei Mihnea

IPC分类号： G11C11/34

CPC分类号： G11C16/0475 ,  G11C16/0466 ,  G11C16/10

摘要： A nitride read only memory (NROM) cell can be programmed by applying a ramp voltage to the gate input, a constant voltage to one of the two source/drain regions, and a ground potential to the remaining source/drain region. In order to erase the NROM cell, a constant voltage is coupled to the gate input. A constant positive current is input to one of the source/drain regions. The remaining source/drain region is either allowed to float, is coupled to a ground potential, or is coupled to the first source/drain region.

摘要翻译： 氮化物只读存储器（NROM）单元可以通过向栅极输入施加斜坡电压，对两个源极/漏极区中的一个施加恒定电压，并将剩余的源极/漏极区的接地电位编程。 为了擦除NROM单元，将恒定电压耦合到栅极输入端。 恒定的正电流被输入到源/漏区之一。 剩余的源极/漏极区域被允许浮动，耦合到接地电位，或耦合到第一源极/漏极区域。

公开(公告)号：US07259996B2

公开(公告)日：2007-08-21

申请号：US11219020

申请日：2005-09-01

申请人： Andrei Mihnea ,  Chun Chen

发明人： Andrei Mihnea ,  Chun Chen

IPC分类号： G11C16/04

CPC分类号： G11C16/16 ,  G11C16/08 ,  G11C16/14 ,  H01L27/115

摘要： Flash memory supporting methods for erasing memory cells using a decrease in magnitude of a source voltage of a first polarity to increase the magnitude of a control gate voltage of a second polarity during an erase period.

公开(公告)号：US20070164348A1

公开(公告)日：2007-07-19

申请号：US11706587

申请日：2007-02-15

申请人： Chun Chen ,  Andrei Mihnea ,  Kirk Prall

发明人： Chun Chen ,  Andrei Mihnea ,  Kirk Prall

IPC分类号： H01L29/788

CPC分类号： H01L27/11519 ,  H01L27/115 ,  H01L27/11521

摘要： Floating-gate field-effect transistors or memory cells formed in isolated wells are useful in the fabrication of non-volatile memory arrays and devices. A column of such floating-gate memory cells are associated with a well containing the source/drain regions for each memory cell in the column. These wells are isolated from source/drain regions of other columns of the array. Fowler-Nordheim tunneling can be used to program and erase such floating-gate memory cells either on an individual basis or on a bulk or block basis.

摘要翻译： 在隔离阱中形成的浮栅场效应晶体管或存储单元在制造非易失性存储器阵列和器件中是有用的。 这种浮栅存储器单元的列与包含列中的每个存储器单元的源极/漏极区的阱相关联。 这些阱与阵列的其他列的源/漏区隔离。 可以使用Fowler-Nordheim隧道来编程和擦除这种浮动栅极存储器单元，无论是单独的还是以块或块为基础的。

公开(公告)号：US07212435B2

公开(公告)日：2007-05-01

申请号：US10881951

申请日：2004-06-30

申请人： Paul J. Rudeck ,  Andrei Mihnea ,  Andrew Bicksler

发明人： Paul J. Rudeck ,  Andrei Mihnea ,  Andrew Bicksler

IPC分类号： G11C16/04 ,  G11C16/06

CPC分类号： G11C16/10 ,  G11C16/0483 ,  G11C16/3418 ,  G11C16/3427

摘要： A selected wordline that is coupled to cells for programming is biased with a programming voltage. The unselected wordlines that are adjacent to the selected wordline are biased at a first predetermined voltage. The remaining wordlines are biased at a second predetermined voltage that is greater than the first predetermined voltage. The first predetermined voltage is selected by determining what unselected, adjacent wordline bias voltage produces a minimized Vpass disturb in response to the selected wordline programming voltage.

摘要翻译： 耦合到用于编程的单元的所选字线被编程电压偏置。 与所选字线相邻的未选字线被偏置在第一预定电压。 剩余的字线被偏置在大于第一预定电压的第二预定电压。 通过确定什么未选择的相邻字线偏置电压响应于所选择的字线编程电压产生最小化的Vcc通道干扰来选择第一预定电压。

公开(公告)号：US07203098B2

公开(公告)日：2007-04-10

申请号：US11215963

申请日：2005-08-31

申请人： Andrei Mihnea ,  Chun Chen

发明人： Andrei Mihnea ,  Chun Chen

IPC分类号： G11C16/04

CPC分类号： G11C16/16 ,  G11C16/08 ,  G11C16/14 ,  H01L27/115

摘要： Methods for erasing flash memory using a decrease in magnitude of a source voltage of a first polarity to increase the magnitude of a control gate voltage of a second polarity during an erase period.

摘要翻译： 使用第一极性的源极电压的幅度的减小来擦除闪存的方法，以在擦除周期期间增加第二极性的控制栅极电压的幅度。