公开(公告)号：US20060090946A1

公开(公告)日：2006-05-04

申请号：US10904279

申请日：2004-11-02

Applicant: David Zhao ,  Leonard Shaner ,  James Cheng

Inventor： David Zhao ,  Leonard Shaner ,  James Cheng

IPC: B60R21/00

CPC classification number: B60R22/02 ,  B60R21/18 ,  B60R21/23138 ,  B60R22/195 ,  B60R22/46 ,  B60R2021/0006 ,  B60R2022/027 ,  B60R2022/4609

Abstract: A safety restraint system (10) for a vehicle (12) includes a seat belt buckle (60) and a retractor (53) mounted approximately at or below a pelvic level of a vehicle occupant (98). A seat belt (52) extends over a side pelvic portion (97) of vehicle occupant (98) and directly prevents outward lateral displacement of the side pelvic portion (97) during a side collision event.

Abstract translation: 一种用于车辆（12）的安全约束系统（10）包括安装带扣（60）和大致在车辆乘员（98）的骨盆水平面上或下方安装的牵开器（53）。 安全带（52）在车辆乘员（98）的侧盆部（97）上延伸，并且在侧面碰撞事件期间直接防止侧盆部（97）的向外侧向移位。

公开(公告)号：US20050013316A1

公开(公告)日：2005-01-20

申请号：US10692269

申请日：2003-10-23

Applicant: Raymond Liao ,  James Cheng

Inventor： Raymond Liao ,  James Cheng

IPC: H04L12/28 ,  H04L12/56 ,  H04L12/42

CPC classification number: H04L47/805 ,  H04L47/14 ,  H04L47/15 ,  H04L47/70 ,  H04L47/788 ,  H04L47/808 ,  H04L47/822 ,  H04L47/824 ,  H04L47/828 ,  H04W28/10 ,  H04W84/12

Abstract: A system, method, apparatus, means, and computer program code for providing a delay guarantee for a wireless network is provided.

Abstract translation: 提供了一种用于为无线网络提供延迟保证的系统，方法，装置，装置和计算机程序代码。

公开(公告)号：US06567075B1

公开(公告)日：2003-05-20

申请号：US09272957

申请日：1999-03-19

Applicant: Albert D. Baker ,  Christine Cook ,  James Cheng-ping Liu ,  Stephen M. Milton ,  David Graham Neale

Inventor： Albert D. Baker ,  Christine Cook ,  James Cheng-ping Liu ,  Stephen M. Milton ,  David Graham Neale

IPC: G06F314

CPC classification number: H04M1/7258

Abstract: Feature access control is provided for soft-labeled keys (SLKs) of a wireless terminal or other type of terminal in a communication system. In an illustrative embodiment, a different set of SLK label identifiers are associated in a control table with each state in a set of states of the terminal. Each of the label identifiers specifies a label to be associated with a given one of the SLKs in a given one of the states. The label identifiers are used as pointers into a label table which specifies, for each of the label identifiers, a corresponding label for one of the SLKs. The control table and label table together implement a bidirectional mapping between single switch-based features and corresponding multiple state-based appearances of those features on the terminal. The control table and label table may be downloaded into the terminal from a switch of the system. The SLK labels of the terminal may be updated by, e.g., transmitting to the terminal a state identifier, an identifier of a most-recently activated feature, and a presentation attribute for that feature.

Abstract translation: 为通信系统中的无线终端或其他类型的终端的软标签密钥（SLK）提供特征访问控制。 在说明性实施例中，不同的SLK标签标识符集合在控制表中与终端的一组状态中的每个状态相关联。 每个标签标识符指定要在给定的一个状态中与给定的一个SLK相关联的标签。 标签标识符用作标签表中的指针，该标签表针对每个标签标识符指定一个SLK的对应标签。 控制表和标签表一起实现了基于单个交换机的功能和终端上这些功能的相应的多个基于状态的外观之间的双向映射。 控制表和标签表可以从系统的开关下载到终端中。 可以通过例如向终端发送状态标识符，最近激活的特征的标识符以及该特征的呈现属性来更新终端的SLK标签。

公开(公告)号：US06365325B1

公开(公告)日：2002-04-02

申请号：US09247791

申请日：1999-02-10

Applicant: Min-Hsiung Chiang ,  Huan-Just Lin ,  James Cheng-Ming Wu ,  Cheng-Tung Lin

Inventor： Min-Hsiung Chiang ,  Huan-Just Lin ,  James Cheng-Ming Wu ,  Cheng-Tung Lin

IPC: G03C500

CPC classification number: G03F7/40

Abstract: A method for fabricating a microelectronic layer. There is first provided a substrate. There is then formed over the substrate a target layer. There is then formed upon the target layer a patterned photoresist layer which defines a first aperture, where the first aperture has a first aperture width which exposes a first portion of the target layer. There is then reflowed thermally the patterned photoresist layer to form a reflowed patterned photoresist layer which defines a substantially straight sided second aperture. The second aperture has a second aperture width less than the first aperture width, and the second aperture thus exposes a second portion of the blanket target layer of areal dimension less than the first portion of the blanket target layer. Finally, there is then fabricated the target layer to form a fabricated target layer while employing the reflowed patterned photoresist layer as a mask layer. The method is useful insofar as it allows the target layer to be fabricated while avoiding the use of advanced microelectronic fabrication photolithographic tooling when forming the patterned photoresist layer.

Abstract translation: 一种制造微电子层的方法。 首先提供基板。 然后在衬底上形成靶层。 然后在目标层上形成限定第一孔的图案化光致抗蚀剂层，其中第一孔具有暴露目标层的第一部分的第一孔宽度。 然后将图案化的光致抗蚀剂层热回流以形成限定基本上直的第二孔的回流图案化光致抗蚀剂层。 第二孔径具有小于第一孔径宽度的第二孔径宽度，并且第二孔口因此暴露了覆盖层目标层的面积尺寸小于覆盖层目标层的第一部分的第二部分。 最后，然后制造目标层以形成制造的目标层，同时使用回流图案化的光致抗蚀剂层作为掩模层。 该方法是有用的，只要它允许制造目标层，同时避免在形成图案化的光致抗蚀剂层时使用先进的微电子制造光刻工具。

公开(公告)号：USD442199S1

公开(公告)日：2001-05-15

申请号：US29122673

申请日：2000-05-02

Applicant: James Cheng

Designer： James Cheng

公开(公告)号：US6159786A

公开(公告)日：2000-12-12

申请号：US210702

申请日：1998-12-14

Applicant: Min-Hsiung Chiang ,  James Cheng-Ming Wu ,  Jenn-Ming Huang

Inventor： Min-Hsiung Chiang ,  James Cheng-Ming Wu ,  Jenn-Ming Huang

IPC: H01L21/3105 ,  H01L21/8242 ,  H01L21/8234 ,  H01L21/8244

CPC classification number: H01L27/10852 ,  H01L21/31055 ,  H01L27/10894

Abstract: A new method of maintaining good control of the dielectric thickness over a top capacitor plate during planarization by CMP by introducing a CMP stop layer under the topmost dielectric layer is described. Semiconductor device structures, including a node contact region, are provided in and on a semiconductor substrate. A bottom plate electrode is formed contacting the node contact region through an opening in a first insulating layer. A capacitor dielectric layer is deposited overlying the bottom plate electrode. A second conducting layer is deposited overlying the capacitor dielectric to form a top plate electrode of the capacitor. A second insulating layer is deposited overlying the second conducting layer. A silicon nitride polish stop layer is deposited overlying the second insulating layer. The polish stop layer, second insulating layer, second conducting layer, and capacitor dielectric layer are patterned to form the DRAM integrated circuit device. A third insulating layer is deposited overlying the first insulating layer and the polish stop layer of the DRAM integrated circuit device. The third insulating layer is planarized by chemical mechanical polishing stopping at the polish stop layer. The polish stop layer protects the top capacitor plate from damage.

Abstract translation: 描述了在通过CMP平坦化期间在顶部电容器板上保持对电介质厚度的良好控制的新方法，其中在最下面的介电层下面引入CMP停止层。 包括节点接触区域的半导体器件结构被提供在半导体衬底中和半导体衬底上。 通过第一绝缘层中的开口形成接触节点接触区域的底板电极。 电容器电介质层沉积在底板电极上。 沉积在电容器电介质上的第二导电层以形成电容器的顶板电极。 沉积在第二导电层上的第二绝缘层。 沉积覆盖在第二绝缘层上的氮化硅抛光停止层。 对抛光停止层，第二绝缘层，第二导电层和电容器电介质层进行构图以形成DRAM集成电路器件。 沉积在DRAM集成电路器件的第一绝缘层和抛光停止层上的第三绝缘层。 通过在抛光停止层处的化学机械抛光停止将第三绝缘层平坦化。 抛光停止层保护顶部电容器板免受损坏。

公开(公告)号：US06015733A

公开(公告)日：2000-01-18

申请号：US133356

申请日：1998-08-13

Applicant: Yu-Hua Lee ,  James (Cheng-Ming) Wu

Inventor： Yu-Hua Lee ,  James (Cheng-Ming) Wu

IPC: H01L21/8242 ,  H01L27/108

CPC classification number: H01L27/10852 ,  H01L27/10817 ,  Y10S438/97

Abstract: A process for forming a crown shaped, polysilicon storage node structure, for a DRAM capacitor structure, has been developed. The process features the deposition of a polysilicon layer, on the top surface of a thick insulator layer, as well as on all surfaces of an opening, in the thick insulator layer. Removal of the regions of polysilicon, residing on the top surface of the thick insulator layer, results in a crown shaped, polysilicon storage node structure, in the opening, in the thick insulator layer. The crown shaped, polysilicon storage node structure, was protected from the polysilicon removal procedure, by a photoresist plug, formed overlying the polysilicon layer, in the opening, in the thick insulator layer. The photoresist plug was formed via photoresist application, exposure, and the development of exposed photoresist regions.

Abstract translation: 已经开发了用于形成用于DRAM电容器结构的冠形多晶硅存储节点结构的工艺。 该工艺的特征在于，在厚的绝缘体层中，在厚的绝缘体层的顶表面以及开口的所有表面上沉积多晶硅层。 在厚的绝缘体层中，去除驻留在厚绝缘体层的顶表面上的多晶硅区域，导致在开口中的冠状多晶硅存储节点结构。 通过在厚的绝缘体层中的开口中形成在多晶硅层上的光致抗蚀剂塞，保护了冠状多晶硅存储节点结构的多晶硅去除程序。 通过光致抗蚀剂施加，曝光和曝光的光致抗蚀剂区域的显影来形成光致抗蚀剂插塞。

公开(公告)号：US6013550A

公开(公告)日：2000-01-11

申请号：US169436

申请日：1998-10-09

Applicant: Yu-Hua Lee ,  James Cheng-Ming Wu

Inventor： Yu-Hua Lee ,  James Cheng-Ming Wu

IPC: H01L21/8242 ,  H01L27/108

CPC classification number: H01L27/10852 ,  H01L27/10817 ,  Y10S438/97

Abstract: A process for forming a crown shaped storage node structure, for a DRAM capacitor structure, has been developed. The process features the patterning of a top portion, of a storage node contact plug structure, after patterning of the crown shaped storage node structure, and after removal of a silicon oxide layer, used for the definition of the crown shaped storage node structure. The sequence of patterning steps allows mis-alignment between the crown shaped storage node structure, and the underlying storage node contact hole, to occur without vulnerability to insulator layers used to passivate the transfer gate transistors, of the DRAM cell. This process also features the use of a photoresist plug, used to protect a bottom shape, of the crown shaped storage node structure during the crown shaped storage node, and the storage node contact plug structure, patterning procedures.

Abstract translation: 已经开发了用于形成用于DRAM电容器结构的冠形存储节点结构的工艺。 该方法的特征在于在图案化冠形存储节点结构之后，以及在去除用于定义冠形存储节点结构的氧化硅层之后的顶部，存储节点接触插塞结构的图案化。 图案化步骤的顺序允许在DRAM单元的绝缘体层被用来钝化传输栅极晶体管的情况下，冠状存储节点结构和下面的存储节点接触孔之间的错误对准发生。 该方法还特征在于在冠形存储节点期间使用用于保护顶部形状的顶部形状的储存节点结构的光致抗蚀剂插塞以及存储节点接触插塞结构，图案化程序。

公开(公告)号：USD393247S

公开(公告)日：1998-04-07

申请号：US066815

申请日：1997-02-21

Applicant: James Cheng

Designer： James Cheng

公开(公告)号：USD388772S

公开(公告)日：1998-01-06

申请号：US67213

申请日：1997-02-21

Applicant: James Cheng

Designer： James Cheng