Cable tester
    101.
    发明授权
    Cable tester 有权
    电缆测试仪

    公开(公告)号:US07019533B1

    公开(公告)日:2006-03-28

    申请号:US11129203

    申请日:2005-05-13

    IPC分类号: G01R31/02 G01R31/11

    摘要: A physical layer device communicates over a cable and includes a cable tester that determines a cable status. The cable tester includes a pretest module that senses activity on the cable. A test module transmits a test pulse on the cable, measures reflection amplitude, calculates a cable length, and determines the cable status based on the measured amplitude and the calculated cable length. A first digital signal processor (DSP) communicates with a first pair of the cable and includes a first echo canceller and a first finite impulse response filter with first taps. A second DSP communicates with a second pair of the cable and includes a second echo canceller and a second finite impulse response filter with second taps. At least one of the physical layer device and the cable tester estimates skew between the first and second pairs based on values of the first and second taps.

    摘要翻译: 物理层设备通过电缆进行通信,并且包括确定电缆状态的电缆测试器。 电缆测试仪包括一个预测试模块,用于检测电缆上的活动。 测试模块在电缆上传输测试脉冲,测量反射幅度,计算电缆长度,并根据测量的幅度和计算的电缆长度确定电缆状态。 第一数字信号处理器(DSP)与第一对电缆通信,并且包括第一回波消除器和具有第一抽头的第一有限脉冲响应滤波器。 第二DSP与第二对电缆通信,并且包括第二回波消除器和具有第二抽头的第二有限脉冲响应滤波器。 物理层设备和电缆测试仪中的至少一个基于第一和第二抽头的值来估计第一对和第二对之间的偏差。

    Cable tester
    102.
    发明授权
    Cable tester 有权
    电缆测试仪

    公开(公告)号:US07005861B1

    公开(公告)日:2006-02-28

    申请号:US10401221

    申请日:2003-03-27

    IPC分类号: G01R31/11

    CPC分类号: G01R31/021 G01R31/11

    摘要: A physical layer device is provided that includes an autonegotiation circuit that negotiates a link with a link partner at first and second link speeds. The physical layer device also includes a cable tester that tests a cable and that determines a cable status of the cable before autonegotiation circuit negotiates the link at the first and second link speeds.

    摘要翻译: 提供了物理层设备,其包括在第一和第二链路速度下协商与链路伙伴的链路的自动协商电路。 物理层设备还包括测试电缆的电缆测试器,并且在自动协商电路以第一和第二链路速度协商链路之前确定电缆的电缆状态。

    Cable tester with insertion loss and return loss estimators
    103.
    发明授权
    Cable tester with insertion loss and return loss estimators 有权
    带插入损耗和回波损耗估计器的电缆测试仪

    公开(公告)号:US06980007B1

    公开(公告)日:2005-12-27

    申请号:US10400367

    申请日:2003-03-27

    IPC分类号: G01R31/08 G01R31/11

    摘要: A physical layer device that communicates over a cable comprises a cable tester that determines a cable status, which includes an open status, a short status, and a normal status. The cable tester includes a pretest module that senses activity on the cable and selectively enables testing based on the sensed activity. A test module is enabled by the pretest module, transmits a test pulse on the cable, measures a reflection amplitude, calculates a cable length, and determines the cable status based on the measured amplitude and the calculated cable length. An insertion loss estimator communicates with the cable tester and estimates insertion loss of the cable. A return loss estimator communicates with the cable tester and estimates return loss of the cable based on gain parameters of the physical layer device.

    摘要翻译: 通过电缆进行通信的物理层设备包括电缆测试器,其确定电缆状态,其包括打开状态,短状态和正常状态。 电缆测试仪包括一个预测试模块,用于检测电缆上的活动,并根据感测到的活动选择性地进行测试。 测试模块由预测试模块启用,在电缆上传输测试脉冲,测量反射幅度,计算电缆长度,并根据测量的幅度和计算出的电缆长度确定电缆状态。 插入损耗估计器与电缆测试仪通信,并估计电缆的插入损耗。 回波损耗估计器与电缆测试仪通信,并根据物理层设备的增益参数估计电缆的回波损耗。

    Methods, software, circuits and systems for coding information
    104.
    发明授权
    Methods, software, circuits and systems for coding information 有权
    用于编码信息的方法,软件,电路和系统

    公开(公告)号:US06956510B1

    公开(公告)日:2005-10-18

    申请号:US10940855

    申请日:2004-09-13

    IPC分类号: H03M5/00 H03M5/14 H04L1/00

    摘要: Methods, software, circuits, architectures, and systems for encoding, decoding and error checking/correcting information, particularly pulse amplitude modulated information. The present invention enjoys particular advantage when used to encode x-unit sequence values of N-ary information into y-unit sequence values of M-ary information and to decode y-unit sequence values of M-ary information into x-unit sequence values of N-ary information, where Nx My−M). The present invention advantageously provides a straight-forward mechanism for coding information that enables one to take advantage of coding overhead (e.g., unused states in the encoded, transmitted sequence) to accomplish other coding objectives, such as conforming to coding constraints, reducing transmission errors (or increasing the likelihood of successfully correcting such errors), dc balancing the coded information, and under certain conditions, even reducing power consumption.

    摘要翻译: 用于编码,解码和错误检查/校正信息的方法,软件,电路,架构和系统,特别是脉冲幅度调制信息。 本发明在用于将N元信息的x单元序列值编码为M元信息的y单元序列值并将M元信息的y单元序列值解码为x单元序列值时具有特别的优点 的N元信息,其中N (特别是其中N S < 但是N M S-M)。 本发明有利地提供了一种用于编码信息的直接机制,其使得能够利用编码开销(例如,编码的,发送的序列中的未使用状态)来实现其他编码目标,诸如符合编码约束,减少传输错误 (或增加成功校正这种错误的可能性),直流平衡编码信息,并且在某些条件下甚至降低功耗。

    Receiver with dual D.C. noise cancellation circuits
    105.
    发明授权
    Receiver with dual D.C. noise cancellation circuits 有权
    具有双路直流消除电路的接收器

    公开(公告)号:US06856790B1

    公开(公告)日:2005-02-15

    申请号:US09536120

    申请日:2000-03-27

    申请人: Runsheng He

    发明人: Runsheng He

    IPC分类号: H04B1/30 H04L25/06 H04B15/00

    CPC分类号: H04B1/30 H04L25/063

    摘要: A circuit employing dual adaptive D.C. noise cancellation loops to eliminate D.C. noise from a signal received from a communication channel. The circuit employing the two adaptive D.C. noise cancellation loops is constructed such that the two adaptive D.C. noise cancellation loops are decoupled to insured stability of the circuit while eliminating the D.C. noise components from a signal received from a communication channel. A first D.C. noise canceler generates a first D.C. noise cancellation signal that is a product of an error signal that is an estimate of noise within the signal and a first D.C. gain constant. The first D.C. Noise is connected within the receiver to an input of a decision circuit that subtractively combines the first D.C. noise cancellation signal with the signal to remove a first portion of the D.C. noise components. A second D.C. noise canceler additively restores the first D.C. noise cancellation signal to the error signal and multiplies the restored error signal with the first D.C. noise cancellation signal by a second D.C. gain constant. The second D.C. noise canceler is connected to the input of the receiver to subtractively combine the received signal acquired from the communication channel with the second D.C. noise cancellation signal to remove a second portion of the D.C. noise components.

    摘要翻译: 一种采用双自适应直流消除环路的电路,以消除从通信信道接收的信号中的直流干扰。 采用两个自适应直流噪声消除环路的电路被构造成使得两个自适应干扰消除环路被去耦合到电路的保险稳定性,同时从通信信道接收的信号中消除直流噪声分量。 第一直流干扰消除器产生第一直流噪声消除信号,其是作为信号内的噪声的估计的误差信号和第一直流增益常数的乘积。 第一直流噪声在接收机内连接到判决电路的输入端,该判决电路将第一直流噪声消除信号与该信号相减,以去除直流噪声分量的第一部分。 第二直流噪声消除器将第一直流干扰消除信号加到误差信号中,并将恢复的误差信号与第一直流干扰消除信号乘以第二直流增益常数。 第二直流噪声消除器连接到接收机的输入端,以将从通信信道获取的接收信号与第二直流噪声消除信号相减,以去除直流干扰分量的第二部分。

    Implementing reduced-state viterbi detectors
    106.
    发明授权
    Implementing reduced-state viterbi detectors 失效
    实现降态维特比探测器

    公开(公告)号:US06711213B2

    公开(公告)日:2004-03-23

    申请号:US10347889

    申请日:2003-01-21

    IPC分类号: H04L512

    摘要: A method of design and an implementation system for reduced-state Viterbi detectors for intersymbol interference channels are provided. The method uses a complement states grouping technique that comprises the steps of finding the state distances between complement states; forming the reduced-state trellis by grouping the complement states with state distance no less than the minimum free distance; and by keeping the complement states with state distance less than minimum free distance unchanged. The resultant reduced-state Viterbi detector has negligible performance loss compared to the full-state Viterbi detector while the complexity is reduced by a factor of about two.

    摘要翻译: 提供了一种用于符号间干扰信道的简化状态维特比检测器的设计方法和实现系统。 该方法使用补码状态分组技术,其包括找到补码状态之间的状态距离的步骤; 通过将状态距离不小于最小自由距离分组补码状态来形成缩小状态网格; 并保持状态距离小于最小自由距离不变的补码状态。 所得到的降维态维特比检测器与全状态维特比检测器相比具有可忽略的性能损失,而复杂度降低了约两倍。

    HIGH-SPEED PARALLEL DECISION FEEDBACK EQUALIZER
    107.
    发明申请
    HIGH-SPEED PARALLEL DECISION FEEDBACK EQUALIZER 有权
    高速并行决策反馈均衡器

    公开(公告)号:US20140056346A1

    公开(公告)日:2014-02-27

    申请号:US13594595

    申请日:2012-08-24

    IPC分类号: H04L27/01

    摘要: A decision-feedback equalizer (DFE) can be operated at higher frequencies when parallelization and pre-computation techniques are employed. Disclosed herein is a DFE design suitable for equalizing receive signals with bit rates above 10 GHz, making it feasible to employ decision feedback equalization in silicon-based optical transceiver modules. One illustrative embodiment includes a front end filter to reduce leading intersymbol interference in a receive signal; a serial-to-parallel converter and at least one pre-compensation unit that together convert the filtered signal into grouped sets of tentative decisions, the sets in each group being made available in parallel; a set of pipelined DFE multiplexer units to select a contingent symbol decision from each set of tentative decisions to form groups of contingent symbol decisions based on a presumed sequence of preceding symbol decisions; and an output multiplexer that chooses, based on preceding symbol decisions, one of said groups of contingent symbol decisions.

    摘要翻译: 当采用并行化和预计算技术时,判决反馈均衡器(DFE)可以以更高的频率运行。 这里公开了一种DFE设计,其适用于均衡接收信号,比特率高于10GHz,使得在硅基光收发器模块中采用判决反馈均衡是可行的。 一个说明性实施例包括前端滤波器以减少接收信号中的前导符号间干扰; 串行到并行转换器和至少一个预补偿单元,其将滤波的信号一起转换成分组的一组暂定决定,每组中的组并行可用; 一组流水线DFE多路复用器单元,用于从每组暂定决定中选择或有符号决定,以基于先前符号决定的推定序列形成组合的偶然符号决定; 以及输出多路复用器,其基于先前的符号判定来选择所述组的偶然符号决定中的一个。

    Feedforward equalizer for DFE based detector
    108.
    发明授权
    Feedforward equalizer for DFE based detector 有权
    用于基于DFE的检测器的前馈均衡器

    公开(公告)号:US08031765B1

    公开(公告)日:2011-10-04

    申请号:US12283664

    申请日:2008-09-15

    申请人: Runsheng He

    发明人: Runsheng He

    IPC分类号: H03H7/30 H04B1/10 G06F17/10

    CPC分类号: H04L25/03057 H04L25/0307

    摘要: A system includes a first filter that receives an input signal and comprises N taps to filter postcursor inter-symbol interference (ISI) of the input signal. S taps of the N taps have a coefficient that is limited between −1 and 0. S and N are integer values greater than or equal to 1. N is greater than or equal to S. A decision feedback equalizer includes a decision circuit that communicates with the first filter. A second filter communicates with an input and an output of the decision circuit.

    摘要翻译: 系统包括接收输入信号并包括N个抽头以滤除输入信号的后符号间干扰(ISI)的第一滤波器。 N个抽头的S个抽头具有限制在-1和0之间的系数.S和N是大于或等于1的整数。N大于或等于S.判决反馈均衡器包括一个决定电路, 与第一个过滤器。 第二滤波器与判决电路的输入和输出通信。

    Input/output data rate synchronization using first in first out data buffers
    109.
    发明授权
    Input/output data rate synchronization using first in first out data buffers 有权
    使用先进先出的数据缓冲器进行输入/输出数据速率同步

    公开(公告)号:US07924960B1

    公开(公告)日:2011-04-12

    申请号:US12574133

    申请日:2009-10-06

    IPC分类号: H04L7/00

    摘要: A system includes a first buffer configured to receive data at a first rate, and output the data at a second rate. A processing module configured to receive the data from the first buffer at the second rate, convert the data into processed data, and output the processed data at a third rate. A second buffer is configured to receive the processed data from the processing module at the third rate, and output the processed data at a fourth rate. The third rate is faster than the fourth rate to avoid a buffer underflow condition in the second buffer. In response to the second buffer reaching a predetermined capacity, the processing module is further configured to enter into a break state in which the processing module temporarily stops both receiving data from the first buffer and outputting the processed data and adjusts the second rate to avoid a buffer overrun condition in the first buffer.

    摘要翻译: 系统包括被配置为以第一速率接收数据的第一缓冲器,并以第二速率输出数据。 一种处理模块,被配置为以第二速率从第一缓冲器接收数据,将数据转换成经处理的数据,并以第三速率输出处理后的数据。 第二缓冲器被配置为以第三速率从处理模块接收处理的数据,并以第四速率输出处理的数据。 第三速率比第四速率快,以避免第二缓冲器中的缓冲器下溢条件。 响应于第二缓冲器达到预定容量,处理模块还被配置为进入中断状态,其中处理模块暂时停止从第一缓冲器接收数据并输出处理后的数据并调整第二速率以避免 缓冲区溢出条件在第一个缓冲区。

    Cable tester
    110.
    发明授权
    Cable tester 有权
    电缆测试仪

    公开(公告)号:US07884615B1

    公开(公告)日:2011-02-08

    申请号:US12082964

    申请日:2008-04-15

    IPC分类号: G01R31/11

    CPC分类号: H04L43/50 G01R31/11 H04L12/10

    摘要: A network interface includes a physical layer (PHY) device that provides an interface to a cable. The PHY device includes an autonegotiation module that selectively performs autonegotiation to establish a link with a link partner based on link parameters and a cable test module that performs a cable test before the autonegotiation begins, that determines a cable performance parameter during the cable test, and that compares the cable performance parameter to a predetermined threshold. The autonegotiation module selects at least one of the link parameters based on the comparison.

    摘要翻译: 网络接口包括提供与电缆的接口的物理层(PHY)设备。 PHY设备包括自动协商模块,所述自动协商模块选择性地执行自动协商以基于链路参数与链路伙伴建立链路,以及在自动协商开始之前执行电缆测试的电缆测试模块,其在电缆测试期间确定电缆性能参数;以及 其将电缆性能参数与预定阈值进行比较。 自动协商模块基于比较选择至少一个链路参数。