Abstract:
A shift register unit, gate driving device, display device and driving method are provided. The shift register unit includes: an input circuit, configured to control a potential of a pull-up control node based on an input signal; a pull-down control circuit, configured to control a potential of a pull-down control node based on the input signal and the potential of the pull-up control node when first signal is at a first level; a pull-down circuit, configured to pull down the potential of the pull-up control node based on the potential of the pull-down control node; a pull-up circuit, configured to control an output signal output from a signal output terminal based on the potential of the pull-up control node and the clock signal; and a reset circuit, configured to reset the output signal based on the potential of the pull-down control node when second signal is at a second level.
Abstract:
A shift register, a driving method, a gate driving circuit and a display device are disclosed. The input module controls the potential of the first node. The first reset module controls the potential of the first node. The second reset module controls the potential of the driving signal output terminal. The first output module controls the potential of the driving signal output terminal under the control of the first node. The second output module controls the potential of the driving signal output terminal under the control of the second node. The pull-down driving module controls the potentials of the first node and the second node. Since the node control signal at the node control signal terminal can eliminate the noise on the first node resulting from the change in the first clock signal, the output stability of the shift register can be improved.
Abstract:
A display driving method is provided. The method comprises: determining whether scanning of at least one area of display areas is completed (S1); adjusting light-emitting luminance of display light source corresponding to the at least one area after the scanning of the at least one area is completed, such that display luminance of the at least one area maintains within a specified range to eliminate picture flicker (S2). The display driving method is capable of reducing commendably the change of display luminance of the at least one area by adjusting the light-emitting luminance of display light source corresponding to the at least one area, so that picture flicker caused by over change of the display luminance would be avoided. There are provided a display driving method and apparatus and a display device comprising the display driving apparatus.
Abstract:
The present disclosure relates to a pixel driving circuit, a driving method thereof, and a display apparatus, to realize switch between resolutions of the display apparatus which is driven by the pixel driving circuit. The pixel driving circuit comprises: r first data lines and k second data lines, each of the first data lines has a first switch unit provided thereon, and is connected to q second data lines through a second switch unit, and the first switch unit and the second switch unit are connected to a signal control unit respectively; and the signal control unit is configured to control the first switch unit to be turned on and the second switch unit to be turned off when display is to be performed at a first resolution, and control the first switch unit to be turned off and the second switch unit to be turned on when display is to be performed at a second resolution, wherein the first resolution is greater than the second resolution.
Abstract:
The present disclosure provides a noise scanning method, a noise scanning device and a touch panel. The noise scanning method includes steps of performing a touch scanning operation on the touch panel, performing a noise scanning operation on the plurality of touch driving lines Tx or the plurality of touch sensing lines Rx while performing the touch scanning operation, and acquiring a position of each touch unit on the touch panel in accordance with a result of the touch scanning operation and a result of the noise scanning operation.
Abstract:
Provided are an image display device and an image display method, which is capable of increasing charging period and reducing switching frequency of driving data while performing display device driving. The image display device comprises combined pixels of m columns and n rows, wherein each of the combined pixels comprises a first row of sub-pixels and a second row of sub-pixels beneath the first row of sub-pixels, wherein in a 2D image display mode, both the first rows of sub-pixels and the second rows of sub-pixels in the respective rows of combined pixels are driven and receive 2D display data; and in a 3D image display mode, one row of sub-pixels in the respective rows of combined pixels receives data and the other row of sub-pixels in the respective rows of combined pixels do not receive data.
Abstract:
The embodiments of the present invention provide a driving circuit and a driving method, a GOA unit, a GOA circuit and a display device, to improve the response speed of the circuit and reduce the leakage current. This driving circuit comprises: at least one pull-up/pull-down unit each configured to pull up or pull down a voltage of a controlled node; each pull-up/pull-down unit comprises at least one double-gate transistor, the double-gate transistor is used to accelerate the charge or discharge of the node when being turned on, or is used to reduce the leakage current passing the node when being turned off. The embodiments of the present invention are suitable to be applied to the display production.
Abstract:
A display substrate includes a scan circuit, a first reference signal line in a third region, and at least three clock signal lines arranged in a fourth region. The scan circuit includes a plurality of stages, wherein a respective stage of the scan circuit includes a respective scan unit configured to provide a control signal to at least a row of subpixels. The respective scan unit includes an input subcircuit configured to receive from an input terminal a start signal or an output signal from a previous scan unit of a previous stage, a first processing subcircuit, a second processing subcircuit, and an output subcircuit configured to output an output signal from an output terminal. The output subcircuit includes a first output transistor. The input subcircuit includes a first input transistor and a second input transistor sequentially coupled between an input terminal and a first node.
Abstract:
Provided is a display substrate including a display region and a non-display region. The non-display region is provided with a gate drive circuit, and the gate drive circuit includes a plurality of cascaded shift register units; a shift register unit includes an input sub-circuit and a denoising output sub-circuit. The denoising output sub-circuit is connected with the input sub-circuit, a first group of clock signal lines, and a second group of clock signal lines, and the input sub-circuit is connected with a third group of clock signal lines. The third group of clock signal lines, the input sub-circuit, the first group of clock signal lines, the denoising output sub-circuit, and the second group of clock signal lines are sequentially arranged along a first direction.
Abstract:
A scan circuit having a plurality of stages is provided. A respective stage includes a respective scan unit configured to provide a control signal to at least a row of subpixels. The respective scan unit includes an input subcircuit configured to receive a start signal or an output signal from a previous scan unit, a first processing subcircuit, a second processing subcircuit, and an output subcircuit. The output subcircuit includes a first output transistor. The input subcircuit includes a first input transistor and a second input transistor sequentially coupled between an input terminal and a first node. The first node is coupled to a gate electrode of the first output transistor. The first processing subcircuit includes a first switch transistor and a second switch transistor coupled between the first node and a first reference terminal. The first reference terminal is configured to receive a first reference signal.