公开(公告)号：US20120051305A1

公开(公告)日：2012-03-01

申请号：US13259587

申请日：2009-10-19

申请人： Junhu Wang ,  Wenhuan Wang ,  Bo Sun ,  Yanfeng Guan ,  Li Wang

发明人： Junhu Wang ,  Wenhuan Wang ,  Bo Sun ,  Yanfeng Guan ,  Li Wang

IPC分类号： H04W74/04 ,  H04W72/04

CPC分类号： H04L1/1887 ,  H04L1/1812 ,  H04L1/1896 ,  H04L5/0021

摘要： The present invention discloses a method for retransmitting hybrid automatic based on persistent scheduling. The method includes: a base station sending retransmission attribute information of a persistent scheduling service to a terminal by a control signaling. An HARQ mechanism under a persistent scheduling mode is perfected by defining a retransmission region of the persistent scheduling service, and retransmission data packets are centralized to be transmitted in the retransmission region at a synchronization time, which, compared with the prior art, saves the overhead of resource indication information indicating each retransmission packet.

摘要翻译： 本发明公开了一种基于持续调度重传混合自动的方法。 该方法包括：基站通过控制信令向终端发送持续调度业务的重传属性信息。 通过定义持续调度业务的重传区域来完善持续调度模式下的HARQ机制，并且将重发数据分组集中在同步时间的重传区域中进行发送，与现有技术相比，节省了开销 指示每个重发分组的资源指示信息。

公开(公告)号：US08090068B2

公开(公告)日：2012-01-03

申请号：US12107584

申请日：2008-04-22

申请人： Bo Sun ,  Gurkanwal Singh Sahota ,  Zixiang Yang

发明人： Bo Sun ,  Gurkanwal Singh Sahota ,  Zixiang Yang

IPC分类号： H03D3/24

CPC分类号： H03L7/085 ,  H03L7/18 ,  H03L2207/50

摘要： A system and method are disclosed related to calibrating a power-on gating window for a time-to-digital converter (TDC) of a digital phase locked loop (DPLL). The gating window is calibrated to ensure proper operation of the DPLL, while at the same time operating the TDC in a power efficient manner. In particular, the technique entails setting the width of the TDC gating window to a default value; operating the DPLL until the control loop is substantially locked; decreasing the width of the TDC gating window by a predetermined amount, while monitoring the phase error signal generated by the phase error device of the DPLL; determining the current width of the TDC gating window at substantially a time when the phase error arrives at or crosses a predetermined threshold; and increasing the current width of the TDC gating window by a predetermined amount to build in a margin of error for the operating width of the TDC gating window.

摘要翻译： 公开了一种系统和方法，用于校准数字锁相环（DPLL）的时间 - 数字转换器（TDC）的上电门控窗口。 门控窗口被校准，以确保DPLL的正常运行，同时以高效的方式操作TDC。 特别地，该技术需要将TDC门控窗口的宽度设置为默认值; 操作DPLL直到控制回路基本锁定; 同时监视由DPLL的相位误差装置产生的相位误差信号，将TDC门控窗口的宽度减小预定量; 在相位误差到达或超过预定阈值的时间基本上确定TDC门控窗口的当前宽度; 并且将TDC门控窗口的当前宽度增加预定量以构成TDC门控窗口的操作宽度的误差范围。

公开(公告)号：US08077822B2

公开(公告)日：2011-12-13

申请号：US12111541

申请日：2008-04-29

申请人： Bo Sun ,  Gary John Ballantyne ,  Gurkanwal Singh Sahota

发明人： Bo Sun ,  Gary John Ballantyne ,  Gurkanwal Singh Sahota

IPC分类号： H03D3/24

CPC分类号： H03L7/00 ,  H03L7/0802 ,  H03L2207/50

摘要： An apparatus comprising a programmable frequency device adapted to generate a reference clock selected from a set of distinct frequency clocks, wherein the programmable frequency device is further adapted to maintain the same temporal relationship of the triggering edges of the reference clock when switching between the distinct frequency clocks. The apparatus further comprises a phase locked loop (PLL), such as a digital PLL (DPLL), that uses the selected reference clock to establish a predetermined phase relationship between an input signal and an output signal. By maintaining substantially the same temporal relationship of the reference clock when switching between distinct frequency clocks, the continual and effective operation of the phase locked loop (PLL) is not significantly disturbed while changing the reference clock. This may be used to control the power consumption of the apparatus.

摘要翻译： 一种包括可编程频率装置的装置，其适于产生从一组不同频率时钟中选择的参考时钟，其中所述可编程频率装置还适于在所述不同频率之间切换时维持所述参考时钟的触发边沿的相同的时间关系 时钟。 该装置还包括使用所选择的参考时钟来建立输入信号和输出信号之间的预定相位关系的锁相环（PLL），例如数字PLL（DPLL）。 通过在不同频率时钟之间切换时保持参考时钟的基本相同的时间关系，在改变参考时钟的同时，锁相环（PLL）的连续和有效操作不会受到明显干扰。 这可以用于控制设备的功耗。

公开(公告)号：US08073416B2

公开(公告)日：2011-12-06

申请号：US11924318

申请日：2007-10-25

申请人： Bo Sun ,  Gurkanwal Singh Sahota ,  Yue Wu

发明人： Bo Sun ,  Gurkanwal Singh Sahota ,  Yue Wu

IPC分类号： H04B7/00 ,  H04B1/40

CPC分类号： H03L7/197 ,  H03J7/065 ,  H03L1/00 ,  H03L7/0802 ,  H03L7/0898 ,  H03L7/093 ,  H03L7/107 ,  H03L2207/06

摘要： A local oscillator includes a phase-locked loop. The phase-locked loop includes voltage controlled oscillator (VCO) and a novel VCO control circuit. The VCO control circuit may be programmable and configurable. In one example, an instruction is received onto the VCO control circuit to change the power state of the VCO. The instruction is issued by other circuitry in response to a detected change in RF channel conditions (for example, a change in a signal-to-noise determination) in a cellular telephone. In response, the VCO control circuit outputs control signals that gradually widen the loop bandwidth of the PLL, then gradually change the VCO bias current to change the VCO power state, and then narrow the loop bandwidth of the PLL back to its original bandwidth. The entire process of widening the PLL bandwidth, changing the VCO power state, and narrowing the PLL bandwidth occurs while the PLL remains locked.

摘要翻译： 本地振荡器包括锁相环。 锁相环包括压控振荡器（VCO）和新型VCO控制电路。 VCO控制电路可以是可编程和可配置的。 在一个示例中，在VCO控制电路上接收指令以改变VCO的功率状态。 响应于在蜂窝电话中的RF信道条件（例如，信噪比确定的变化）的检测到的改变，由其他电路发出指令。 作为响应，VCO控制电路输出逐渐拓宽PLL环路带宽的控制信号，然后逐渐改变VCO偏置电流，改变VCO功率状态，然后将PLL的环路带宽缩小回原来的带宽。 当PLL保持锁定时，会发生整个PLL带宽扩大，改变VCO功率状态和缩小PLL带宽的过程。

公开(公告)号：US08044742B2

公开(公告)日：2011-10-25

申请号：US12402441

申请日：2009-03-11

申请人： Bo Sun

发明人： Bo Sun

IPC分类号： H04L27/20

CPC分类号： H04L27/2032 ,  H03C3/00 ,  H03L7/0812 ,  H04L27/205 ,  H04L27/361

摘要： An apparatus for phase modulation includes a delay locked loop configured to generate from a reference signal a plurality of phase shifted signals, each of the phase shifted signals being locked to the reference signal and having a different phase shift from the other phase shifted signals with respect to the reference signal, and a multiplexer configured to select one of the phase shifted signals.

摘要翻译： 一种用于相位调制的装置包括：延迟锁定环路，被配置为从参考信号产生多个相移信号，每个相移信号被锁定到参考信号，并且与其它相移信号具有不同的相移 以及被配置为选择所述相移信号之一的多路复用器。

公开(公告)号：US20110050340A1

公开(公告)日：2011-03-03

申请号：US12558110

申请日：2009-09-11

申请人： Bo Sun ,  Anthony F. Segoria

发明人： Bo Sun ,  Anthony F. Segoria

IPC分类号： H03F1/00

CPC分类号： H03F1/301 ,  H03F1/0283 ,  H03F3/191 ,  H03F3/45183 ,  H03F2203/45544 ,  H03F2203/45562 ,  H03F2203/45652 ,  H04B2001/6908

摘要： An apparatus including cascaded amplification stages adapted to be biased by a common DC current to generate an amplified output signal from an input signal. A first amplification stage includes a routing network to substantially double an input voltage signal, and a first transconductance gain stage to generate a first current signal from the input voltage signal. A second amplification stage includes a resonator to convert the first current signal into a second voltage signal, and a second transconductance gain stage to generate a second current signal from the first current signal. A third amplification stage includes a current gain stage to generate a third current signal from the second current signal, and a load through which the third current signal flows to generate the output signal.

摘要翻译： 一种包括级联放大级的装置，其适于被公共DC电流偏置以从输入信号产生放大的输出信号。 第一放大级包括使输入电压信号基本上加倍的布线网络以及从输入电压信号产生第一电流信号的第一跨导增益级。 第二放大级包括将第一电流信号转换成第二电压信号的谐振器和由第一电流信号产生第二电流信号的第二跨导增益级。 第三放大级包括从第二电流信号产生第三电流信号的电流增益级和第三电流信号通过该负载产生输出信号的负载。

公开(公告)号：US07872543B2

公开(公告)日：2011-01-18

申请号：US12133726

申请日：2008-06-05

申请人： Gary John Ballantyne ,  Arun Jayaraman ,  Bo Sun ,  Gurkanwal Singh Sahota

发明人： Gary John Ballantyne ,  Arun Jayaraman ,  Bo Sun ,  Gurkanwal Singh Sahota

IPC分类号： H04L27/20

CPC分类号： H04L27/362 ,  H03F3/2176

摘要： A bi-polar modulator that can perform quadrature modulation using amplitude modulators is described. In one design, the bi-polar modulator includes first and second amplitude modulators and a summer. The first amplitude modulator amplitude modulates a first carrier signal with a first input signal and provides a first amplitude modulated signal. The second amplitude modulator amplitude modulates a second carrier signal with a second input signal and provides a second amplitude modulated signal. The summer sums the first and second amplitude modulated signals and provides a quadrature modulated signal that is both amplitude and phase modulated. The first and second input signals may be obtained based on absolute values of first and second modulating signals, respectively. The first and second carrier signals have phases determined based on the sign of the first and second modulating signals, respectively. Each amplitude modulator may be implemented with a class-E amplifier.

摘要翻译： 描述了可以使用幅度调制器执行正交调制的双极调制器。 在一种设计中，双极调制器包括第一和第二幅度调制器和夏季。 第一幅度调制器利用第一输入信号调制第一载波信号并提供第一幅度调制信号。 第二幅度调制器利用第二输入信号幅度调制第二载波信号，并提供第二幅度调制信号。 夏季对第一和第二幅度调制信号进行求和，并提供幅度和相位调制的正交调制信号。 可以分别基于第一和第二调制信号的绝对值来获得第一和第二输入信号。 第一和第二载波信号分别基于第一和第二调制信号的符号确定相位。 每个幅度调制器可以用E类放大器来实现。

公开(公告)号：US07808418B2

公开(公告)日：2010-10-05

申请号：US12041403

申请日：2008-03-03

申请人： Bo Sun ,  Zixiang Yang

发明人： Bo Sun ,  Zixiang Yang

IPC分类号： H03M1/50

CPC分类号： G04F10/005

摘要： Techniques for enabling a time-to-digital (TDC) to sample with sub-inverter delay resolution are disclosed. In an embodiment, the inputs to a differential D-Q flip-flop in the TDC are coupled to a single-ended signal and a delayed and inverted version of that signal to allow time interpolation of the signal. Further disclosed are techniques to balance the loads of a first delay line and a complementary delay line within the TDC.

摘要翻译： 公开了一种能够实现时间数字（TDC）采用次逆变器延迟分辨率的技术。 在一个实施例中，TDC中的差分D-Q触发器的输入被耦合到单端信号和该信号的延迟和反相版本，以允许信号的时间插值。 进一步公开的是平衡TDC内的第一延迟线和互补延迟线的负载的技术。

公开(公告)号：US07764127B2

公开(公告)日：2010-07-27

申请号：US11565523

申请日：2006-11-30

申请人： Bo Sun ,  Arun Jayaraman ,  Gary John Ballantyne ,  Gurkanwal S Sahota

发明人： Bo Sun ,  Arun Jayaraman ,  Gary John Ballantyne ,  Gurkanwal S Sahota

IPC分类号： H03B5/12

CPC分类号： H03L7/10 ,  H03B5/1215 ,  H03B5/1228 ,  H03B5/1265 ,  H03L7/099

摘要： This disclosure describes designs for a digitally controlled oscillator (DCO). The DCO can overcome many of the shortcomings associated with conventional voltage controlled oscillators (VCOs), and may improve wireless communication devices. The described DCO may improve the frequency synthesis process, reduce noise in a wireless communication device, and allow for simplification of various components of the device.

摘要翻译： 本公开描述了数字控制振荡器（DCO）的设计。 DCO可以克服与常规压控振荡器（VCO）相关的许多缺点，并且可以改进无线通信设备。 所描述的DCO可以改善频率合成过程，减少无线通信设备中的噪声，并且允许简化设备的各种组件。

公开(公告)号：US20100182090A1

公开(公告)日：2010-07-22

申请号：US12355860

申请日：2009-01-19

申请人： Zixiang Yang ,  Chiewcharn Narathong ,  Bo Sun

发明人： Zixiang Yang ,  Chiewcharn Narathong ,  Bo Sun

IPC分类号： H03F3/16

CPC分类号： H03F3/193 ,  H03F1/3205 ,  H03F1/3211 ,  H03F3/45183 ,  H03F3/72 ,  H03F2200/294 ,  H03F2200/451 ,  H03F2203/45386 ,  H03F2203/45481 ,  H03F2203/7221

摘要： An amplifier for operating at low, middle or high linearity modes, the amplifier comprising a first low noise amplifier (LNA) coupled to a second low noise amplifier for providing amplification; a first degeneration inductor coupled to the first LNA for providing impedance matching; a −g3 generation block coupled to an output of the second LNA for canceling third-order transconductance distortion; and a first enabling/disabling component coupled to the output of the second LNA and aligned in parallel with the −g3 generation block for operating at least one of the first and second LNAs at one of the low, middle or high linearity modes.

摘要翻译： 一种用于在低，中或高线性模式下操作的放大器，所述放大器包括耦合到第二低噪声放大器以提供放大的第一低噪声放大器（LNA） 耦合到第一LNA的第一退化电感器，用于提供阻抗匹配; 耦合到所述第二LNA的输出以消除三阶跨导失真的-g3生成块; 以及耦合到第二LNA的输出并且与-g3生成块并行对准的第一使能/禁用组件，用于在低，中或高线性模式中的一个模式下操作第一和第二LNA中的至少一个。