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101.发明申请BIT INTERLEAVER FOR LOW-DENSITY PARITY CHECK CODEWORD HAVING LENGTH OF 64800 AND CODE RATE OF 2/15 AND 256-SYMBOL MAPPING, AND BIT INTERLEAVING METHOD USING SAME 有权用于低密度奇偶校验的比特交换机检查长度为64800，编码速率为2/15和256符号映射，以及使用相同的比特交换方法公开(公告)号：US20160241263A1
公开(公告)日：2016-08-18
申请号：US14639646
申请日：2015-03-05
Inventor： Sung-Ik PARK , Sun-Hyoung KWON , Jae-Young LEE , Heung-Mook KIM , Nam-Ho HUR
CPC classification number: H03M13/2792 , H03M13/1102 , H03M13/1165 , H03M13/255 , H03M13/2778 , H03M13/6552
Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 2/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 256-symbol mapping.
Abstract translation: 本文公开了一种位交织器，位交织编码调制（BICM）装置和比特交织方法。 比特交织器包括第一存储器，处理器和第二存储器。 第一存储器存储具有长度为64800和码率为2/15的低密度奇偶校验（LDPC）码字。 处理器通过基于比特组交织LDPC码字来产生交错码字。 位组的大小对应于LDPC码字的并行因子。 第二存储器将交织的码字提供给用于256符号映射的调制器。
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102.发明申请BIT INTERLEAVER FOR LOW-DENSITY PARITY CHECK CODEWORD HAVING LENGTH OF 64800 AND CODE RATE OF 2/15 AND 64-SYMBOL MAPPING, AND BIT INTERLEAVING METHOD USING SAME 有权用于低密度奇偶校验的位交换机检查长度为64800，编码速率为2/15和64符号映射，以及使用相同的位交互方法公开(公告)号：US20160241261A1
公开(公告)日：2016-08-18
申请号：US14626272
申请日：2015-02-19
Inventor： Sung-Ik PARK , Sun-Hyoung KWON , Jae-Young LEE , Heung-Mook KIM , Nam-Ho HUR
CPC classification number: H03M13/2792 , H03M13/1102 , H03M13/1148 , H03M13/1165 , H03M13/255 , H03M13/2778 , H04L1/0041 , H04L1/0045 , H04L1/0058 , H04L1/0071
Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 2/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 64-symbol mapping.
Abstract translation: 本文公开了一种位交织器，位交织编码调制（BICM）装置和比特交织方法。 比特交织器包括第一存储器，处理器和第二存储器。 第一存储器存储具有长度为64800和码率为2/15的低密度奇偶校验（LDPC）码字。 处理器通过基于比特组交织LDPC码字来产生交错码字。 位组的大小对应于LDPC码字的并行因子。 第二存储器将交织的码字提供给用于64符号映射的调制器。
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103.发明申请BIT INTERLEAVER FOR LOW-DENSITY PARITY CHECK CODEWORD HAVING LENGTH OF 64800 AND CODE RATE OF 2/15 AND 16-SYMBOL MAPPING, AND BIT INTERLEAVING METHOD USING SAME 有权用于低密度奇偶校验的比特交换机检查长度为64800，编码速率为2/15和16符号映射，以及使用相同的比特交换方法公开(公告)号：US20160241260A1
公开(公告)日：2016-08-18
申请号：US14626169
申请日：2015-02-19
Inventor： Sung-Ik PARK , Sun-Hyoung KWON , Jae-Young LEE , Heung-Mook KIM , Nam-Ho HUR
CPC classification number: H03M13/2792 , H03M13/1102 , H03M13/1165 , H03M13/255 , H03M13/271 , H03M13/2778 , H03M13/616 , H03M13/6552 , H04L1/0041 , H04L1/0058 , H04L1/0071
Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 2/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 16-symbol mapping.
Abstract translation: 本文公开了一种位交织器，位交织编码调制（BICM）装置和比特交织方法。 比特交织器包括第一存储器，处理器和第二存储器。 第一存储器存储具有长度为64800和码率为2/15的低密度奇偶校验（LDPC）码字。 处理器通过基于比特组交织LDPC码字来产生交错码字。 位组的大小对应于LDPC码字的并行因子。 第二存储器将交织的码字提供给用于16符号映射的调制器。
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104.发明申请BIT INTERLEAVER FOR LOW-DENSITY PARITY CHECK CODEWORD HAVING LENGTH OF 64800 AND CODE RATE OF 3/15 AND 64-SYMBOL MAPPING, AND BIT INTERLEAVING METHOD USING SAME 有权用于低密度奇偶校验的比特交换机检查长度为64800，编码速率为3/15和64符号映射，以及使用相同的比特交换方法公开(公告)号：US20160218741A1
公开(公告)日：2016-07-28
申请号：US14625563
申请日：2015-02-18
Inventor： Sung-Ik PARK , Sun-Hyoung KWON , Jae-Young LEE , Heung-Mook KIM , Nam-Ho HUR
CPC classification number: H03M13/2792 , G06F11/1076 , H03M13/1102 , H03M13/1151 , H03M13/1165 , H03M13/255 , H03M13/2739 , H03M13/2778 , H03M13/6552
Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 3/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 64-symbol mapping.
Abstract translation: 本文公开了一种位交织器，位交织编码调制（BICM）装置和比特交织方法。 比特交织器包括第一存储器，处理器和第二存储器。 第一存储器存储长度为64800且码率为3/15的低密度奇偶校验（LDPC）码字。 处理器通过基于比特组交织LDPC码字来产生交错码字。 位组的大小对应于LDPC码字的并行因子。 第二存储器将交织的码字提供给用于64符号映射的调制器。
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105.发明申请APPARATUS FOR BROADCASTING SCALABLE VIDEO CONTENTS AND METHOD USING THE SAME 审中-公开用于广播可扩展视频内容的装置和使用该视频内容的方法公开(公告)号：US20160212458A1
公开(公告)日：2016-07-21
申请号：US14994647
申请日：2016-01-13
Inventor： Sun-Hyoung KWON , Sung-Ik PARK , Jae-Young LEE , Heung-Mook KIM
IPC: H04N21/2343 , H04N21/845 , H04N21/8547 , H04N21/236
CPC classification number: H04N21/234327 , H04N21/8451
Abstract: An apparatus and method for broadcasting scalable video contents are disclosed. An apparatus for broadcasting scalable video contents according to an embodiment of the present invention includes a video codec unit configured to generate a plurality of codec layer signals by dividing codec media stream into a plurality of layers; encapsulation and delivery unit configured to perform a transformation for transferring on the codec layer signals; and broadcasting signal multiplexing unit configured to generate a layered-division-multiplexed broadcasting signal by combining the codec layer signals at different power levels.
Abstract translation: 公开了一种用于广播可分级视频内容的装置和方法。 根据本发明的实施例的用于广播可分级视频内容的装置包括：视频编解码器单元，被配置为通过将编解码器媒体流分成多个层来产生多个编解码器层信号; 封装和传送单元，被配置为执行用于在所述编解码器层上传送信号的变换; 以及广播信号复用单元，被配置为通过组合不同功率电平的编解码器层信号来生成分层复用广播信号。
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Patent Agency Ranking
106.发明申请LOW DENSITY PARITY CHECK ENCODER HAVING LENGTH OF 16200 AND CODE RATE OF 4/15, AND LOW DENSITY PARITY CHECK ENCODING METHOD USING THE SAME 有权低密度奇偶校验编码器的长度为16200，编码速率为4/15，低密度奇偶校验编码方法使用该方法公开(公告)号：US20160049955A1
公开(公告)日：2016-02-18
申请号：US14496375
申请日：2014-09-25
Inventor： Sung-Ik PARK , Heung-Mook KIM , Sun-Hyoung KWON , Nam-Ho HUR
CPC classification number: H03M13/1165 , H03M13/036 , H03M13/2792 , H03M13/6505 , H04L1/0043 , H04L1/0057 , H04L1/0058
Abstract: A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 16200 and a code rate of 4/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).
Abstract translation: 公开了一种低密度奇偶校验（LDPC）编码器，LDPC解码器和LDPC编码方法。 LDPC编码器包括第一存储器，第二存储器和处理器。 第一存储器存储长度为16200且码率为4/15的LDPC码字。 第二存储器被初始化为0.处理器通过使用与奇偶校验矩阵（PCM）相对应的序列执行相对于第二存储器的累积来生成与信息位对应的LDPC码字。
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107.发明申请MODULATOR AND MODULATION METHOD USING NON-UNIFORM 16-SYMBOL SIGNAL CONSTELLATION FOR LOW-DENSITY PARITY CHECK CODEWORD HAVING 3/15 CODE RATE 有权使用非均匀16符号信号的调制器和调制方法用于低密度奇偶校验检查具有3/15代码率的编码公开(公告)号：US20150229335A1
公开(公告)日：2015-08-13
申请号：US14618972
申请日：2015-02-10
Inventor： Sung-Ik PARK , Sun-Hyoung KWON , Jae-Young LEE , Heung-Mook KIM , Nam-Ho HUR
CPC classification number: H03M13/1165 , H03M13/255 , H03M13/2792 , H03M13/616 , H03M13/6552 , H04L1/0041 , H04L1/0042 , H04L1/0057 , H04L1/0058 , H04L1/0071 , H04L27/3422
Abstract: A modulator and a modulation method using a non-uniform 16-symbol signal constellation are disclosed. The modulator includes a memory and a processor. The memory receives a codeword corresponding to a low-density parity check (LDPC) code having a code rate of 3/15. The processor maps the codeword to 16 symbols of the non-uniform 16-symbol signal constellation on a 4-bit basis.
Abstract translation: 公开了一种使用非均匀16符号信号星座的调制器和调制方法。 调制器包括存储器和处理器。 存储器接收与码率为3/15的低密度奇偶校验（LDPC）码对应的码字。 处理器将码字映射为4比特的16位符号的不均匀16符号信号星座。
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108.发明申请LOW DENSITY PARITY CHECK ENCODER HAVING LENGTH OF 64800 AND CODE RATE OF 7/15, AND LOW DENSITY PARITY CHECK ENCODING METHOD USING THE SAME 有权低密度奇偶校验编码器的长度为64800，编码速率为7/15，低密度奇偶校验编码方法使用该方法公开(公告)号：US20150100844A1
公开(公告)日：2015-04-09
申请号：US14496700
申请日：2014-09-25
Inventor： Sung-Ik PARK , Heung-Mook KIM , Sun-Hyoung KWON , Nam-Ho HUR
IPC: H03M13/11
CPC classification number: H03M13/1157 , H03M13/1165 , H03M13/1177 , H03M13/616 , H03M13/618
Abstract: A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 64800 and a code rate of 7/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).
Abstract translation: 公开了一种低密度奇偶校验（LDPC）编码器，LDPC解码器和LDPC编码方法。 LDPC编码器包括第一存储器，第二存储器和处理器。 第一存储器存储长度为64800和码率为7/15的LDPC码字。 第二存储器被初始化为0.处理器通过使用与奇偶校验矩阵（PCM）相对应的序列执行相对于第二存储器的累积来生成与信息位对应的LDPC码字。
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109.发明公开公开(公告)号：US20240323072A1
公开(公告)日：2024-09-26
申请号：US18733581
申请日：2024-06-04
Inventor： Sung-Ik PARK , Jae-Young LEE , Sun-Hyoung KWON , Heung-Mook KIM
IPC: H04L27/26 , H04J11/00 , H04L1/00 , H04L7/08 , H04L65/611
CPC classification number: H04L27/2627 , H04J11/004 , H04L1/0041 , H04L1/0058 , H04L1/0068 , H04L1/0071 , H04L1/0072 , H04L7/08 , H04L27/26 , H04L27/2613 , H04L27/2647 , H04L65/611
Abstract: An apparatus and method for broadcast signal frame using a bootstrap and a preamble are disclosed. An apparatus for generating broadcast signal frame according to an embodiment of the present invention includes a time interleaver configured to generate a time-interleaved signal by performing interleaving on a BICM output signal; and a frame builder configured to generate a broadcast signal frame including a bootstrap and a preamble using the time-interleaved signal.
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110.发明公开公开(公告)号：US20240322842A1
公开(公告)日：2024-09-26
申请号：US18735554
申请日：2024-06-06
Inventor： Sung-Ik PARK , Sun-Hyoung KWON , Jae-Young LEE , Heung-Mook KIM
CPC classification number: H03M13/152 , H03M13/116 , H03M13/1162 , H03M13/1165 , H03M13/271 , H03M13/2778 , H03M13/618 , H03M13/6362 , H03M13/253 , H03M13/255 , H03M13/2906 , H03M13/6393 , H03M13/6552
Abstract: A parity interleaving apparatus and method for variable length signaling information are disclosed. A parity interleaving apparatus according to an embodiment of the present invention includes a processor configured to generate a parity bit string for parity puncturing by segmenting parity bits of an LDPC codeword whose length is 16200 and whose code rate is 3/15, into a plurality of groups, and group-wise interleaving the groups using an order of group-wise interleaving; and memory configured to provide the parity bit string for parity puncturing to a parity puncturing unit.
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