中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

114 records (took 0.045 seconds)

    SM4 acceleration processors, methods, systems, and instructions
    103.
    发明授权
    SM4 acceleration processors, methods, systems, and instructions 有权

    公开(公告)号：US10476667B2

    公开(公告)日：2019-11-12

    申请号：US16147650

    申请日：2018-09-29

    Applicant: Intel Corporation

    Inventor： Shay Gueron ,  Vlad Krasnov

    IPC: H04L29/06 ,  H04L9/06 ,  G06F9/30 ,  G06F21/60

    Abstract: A processor of an aspect includes a plurality of packed data registers, and a decode unit to decode an instruction. The instruction is to indicate one or more source packed data operands. The one or more source packed data operands are to have four 32-bit results of four prior SM4 cryptographic rounds, and four 32-bit values. The processor also includes an execution unit coupled with the decode unit and the plurality of the packed data registers. The execution unit, in response to the instruction, is to store four 32-bit results of four immediately subsequent and sequential SM4 cryptographic rounds in a destination storage location that is to be indicated by the instruction.

    Secure memory
    104.
    发明授权
    Secure memory 有权

    公开(公告)号：US10372625B2

    公开(公告)日：2019-08-06

    申请号：US15391229

    申请日：2016-12-27

    Applicant: Intel Corporation

    Inventor： Rodrigo R. Branco ,  Shay Gueron

    IPC: G06F21/00 ,  G06F12/14 ,  H04L9/06 ,  G06F11/10 ,  G06F21/78 ,  G06F7/58

    Abstract: Various examples are directed to systems and methods for securing a data storage device. A storage controller may receive a read request directed to the data storage device. The read request may comprise address data indicating a first address of a first storage location at the data storage device. The storage controller may request from the data storage device a first encrypted data unit stored at the first memory element and a first encrypted set of parity bits, such as Error Correction Code (ECC) bits, associated with the first storage location. An encryption system may decrypt the first encrypted set of parity bits to generate a first set of parity bits based at least in part on an a first location parity key for the first address.

    INSTRUCTIONS AND LOGIC TO PROVIDE GENERAL PURPOSE GF(256) SIMD CRYPTOGRAPHIC ARITHMETIC FUNCTIONALITY
    110.
    发明申请
    INSTRUCTIONS AND LOGIC TO PROVIDE GENERAL PURPOSE GF(256) SIMD CRYPTOGRAPHIC ARITHMETIC FUNCTIONALITY 审中-公开

    公开(公告)号：US20170272237A1

    公开(公告)日：2017-09-21

    申请号：US15405898

    申请日：2017-01-13

    Applicant: Intel Corporation

    Inventor： Shay Gueron

    IPC: H04L9/06 ,  G06F9/30 ,  G06F9/38 ,  G06F7/00 ,  G06F21/60

    CPC classification number: H04L9/0631 ,  G06F7/00 ,  G06F9/30007 ,  G06F9/30112 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/30196 ,  G06F9/3887 ,  G06F21/602 ,  H04L2209/34

    Abstract: Instructions and logic provide general purpose GF(28) SIMD cryptographic arithmetic functionality. Embodiments include a processor to decode an instruction for a SIMD affine transformation specifying a source data operand, a transformation matrix operand, and a translation vector. The transformation matrix is applied to each element of the source data operand, and the translation vector is applied to each of the transformed elements. A result of the instruction is stored in a SIMD destination register. Some embodiments also decode an instruction for a SIMD binary finite field multiplicative inverse to compute an inverse in a binary finite field modulo an irreducible polynomial for each element of the source data operand. Some embodiments also decode an instruction for a SIMD binary finite field multiplication specifying first and second source data operands to multiply each corresponding pair of elements of the first and second source data operand modulo an irreducible polynomial.

Patent Agency Ranking