公开(公告)号：US10256972B2

公开(公告)日：2019-04-09

申请号：US14984629

申请日：2015-12-30

Applicant: Intel Corporation

Inventor： Shay Gueron ,  Wajdi K Feghali ,  Vinodh Gopal ,  Raghunandan Makaram ,  Martin G Dixon ,  Srinivas Chennupaty ,  Michael E Kounavis

IPC: H04L9/28 ,  G06F21/72 ,  H04L9/06 ,  H04L9/08 ,  G06F12/14 ,  G06F21/60 ,  G06F12/0875 ,  G06F9/30 ,  G06F12/0862 ,  G06F9/38 ,  G11C7/10 ,  G06F3/06

Abstract: A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers.

公开(公告)号：US10256971B2

公开(公告)日：2019-04-09

申请号：US14984601

申请日：2015-12-30

Applicant: Intel Corporation

Inventor： Shay Gueron ,  Wajdi K Feghali ,  Vinodh Gopal ,  Raghunandan Makaram ,  Martin G Dixon ,  Srinivas Chennupaty ,  Michael E Kounavis

IPC: H04L9/28 ,  G06F21/72 ,  H04L9/06 ,  H04L9/08 ,  G06F12/14 ,  G06F21/60 ,  G06F12/0875 ,  G06F9/30 ,  G06F12/0862 ,  G06F9/38 ,  G11C7/10 ,  G06F3/06

Abstract: A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers.

公开(公告)号：US20170364476A1

公开(公告)日：2017-12-21

申请号：US15640395

申请日：2017-06-30

Applicant: Intel Corporation

Inventor： Ronen Zohar ,  Mark Seconi ,  Rajesh Parthasarathy ,  Srinivas Chennupaty ,  Mark Buxton ,  Chuck Desylva ,  Mohammad Abdallah

IPC: G06F17/10 ,  G06F7/48 ,  G06F7/544 ,  G06F9/30

CPC classification number: G06F17/10 ,  G06F7/48 ,  G06F7/5443 ,  G06F9/3001

Abstract: Method, apparatus, and program means for performing a dot-product operation. In one embodiment, an apparatus includes execution resources to execute a first instruction. In response to the first instruction, said execution resources store to a storage location a result value equal to a dot-product of at least two operands.

公开(公告)号：US09772847B2

公开(公告)日：2017-09-26

申请号：US14576136

申请日：2014-12-18

Applicant: Intel Corporation

Inventor： Michael A. Julier ,  Jeffrey D. Gray ,  Srinivas Chennupaty ,  Sean P. Mirkes ,  Mark P. Seconi

IPC: G06F9/30 ,  G06F9/38 ,  G06F7/06 ,  G06F12/0875 ,  G06F9/34

CPC classification number: G06F9/30145 ,  G06F7/06 ,  G06F9/30 ,  G06F9/3001 ,  G06F9/30021 ,  G06F9/30029 ,  G06F9/30036 ,  G06F9/30098 ,  G06F9/30109 ,  G06F9/3013 ,  G06F9/30167 ,  G06F9/3017 ,  G06F9/30185 ,  G06F9/30192 ,  G06F9/34 ,  G06F9/3802 ,  G06F9/3824 ,  G06F9/3853 ,  G06F9/3885 ,  G06F9/3887 ,  G06F12/0875 ,  G06F2212/452

Abstract: Processor to perform a packed comparison instruction. The processor includes a decoder to decode the packed comparison instruction. The packed comparison instruction has an immediate to indicate the comparison operation.

公开(公告)号：US09641320B2

公开(公告)日：2017-05-02

申请号：US14572584

申请日：2014-12-16

Applicant: Intel Corporation

Inventor： Shay Gueron ,  Wajdi K. Feghali ,  Vinodh Gopal ,  Raghunandan Makaram ,  Martin G. Dixon ,  Srinivas Chennupaty ,  Michael E. Kounavis

IPC: H04L9/28 ,  G06F21/72 ,  H04L9/06 ,  H04L9/08 ,  G06F12/14 ,  G06F21/60 ,  G06F12/0875 ,  G06F9/30 ,  G06F12/0862 ,  G06F9/38 ,  G11C7/10 ,  G06F3/06

CPC classification number: H04L9/0631 ,  G06F3/0623 ,  G06F3/0665 ,  G06F3/0689 ,  G06F9/30007 ,  G06F9/30036 ,  G06F9/30047 ,  G06F9/30145 ,  G06F9/30178 ,  G06F9/3802 ,  G06F9/3818 ,  G06F9/3887 ,  G06F9/3895 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/1408 ,  G06F21/602 ,  G06F2212/1052 ,  G06F2212/402 ,  G06F2212/452 ,  G06F2212/454 ,  G06F2212/602 ,  G11C7/1072 ,  H04L9/0816 ,  H04L9/0861 ,  H04L2209/12 ,  H04L2209/24

Abstract: A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers.

公开(公告)号：US09641319B2

公开(公告)日：2017-05-02

申请号：US14572578

申请日：2014-12-16

Applicant: Intel Corporation

Inventor： Shay Gueron ,  Wajdi K. Feghali ,  Vinodh Gopal ,  Raghunandan Makaram ,  Martin G. Dixon ,  Srinivas Chennupaty ,  Michael E. Kounavis

IPC: G06F21/72 ,  H04L9/06 ,  H04L9/08 ,  G06F12/14 ,  G06F21/60 ,  G06F12/0875 ,  G06F9/30 ,  G06F12/0862 ,  G06F9/38 ,  G11C7/10 ,  G06F3/06

CPC classification number: H04L9/0631 ,  G06F3/0623 ,  G06F3/0665 ,  G06F3/0689 ,  G06F9/30007 ,  G06F9/30036 ,  G06F9/30047 ,  G06F9/30145 ,  G06F9/30178 ,  G06F9/3802 ,  G06F9/3818 ,  G06F9/3887 ,  G06F9/3895 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/1408 ,  G06F21/602 ,  G06F2212/1052 ,  G06F2212/402 ,  G06F2212/452 ,  G06F2212/454 ,  G06F2212/602 ,  G11C7/1072 ,  H04L9/0816 ,  H04L9/0861 ,  H04L2209/12 ,  H04L2209/24

Abstract: A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers.

公开(公告)号：US09634828B2

公开(公告)日：2017-04-25

申请号：US14572540

申请日：2014-12-16

Applicant: Intel Corporation

Inventor： Shay Gueron ,  Wajdi K Feghali ,  Vinodh Gopal ,  Raghunandan Makaram ,  Martin G Dixon ,  Srinivas Chennupaty ,  Michael E Kounavis

IPC: H04L9/28 ,  G06F21/72 ,  H04L9/06 ,  H04L9/08 ,  G06F12/14 ,  G06F21/60 ,  G06F12/0875 ,  G06F9/30 ,  G06F12/0862 ,  G06F9/38 ,  G11C7/10 ,  G06F3/06

CPC classification number: H04L9/0631 ,  G06F3/0623 ,  G06F3/0665 ,  G06F3/0689 ,  G06F9/30007 ,  G06F9/30036 ,  G06F9/30047 ,  G06F9/30145 ,  G06F9/30178 ,  G06F9/3802 ,  G06F9/3818 ,  G06F9/3887 ,  G06F9/3895 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/1408 ,  G06F21/602 ,  G06F2212/1052 ,  G06F2212/402 ,  G06F2212/452 ,  G06F2212/454 ,  G06F2212/602 ,  G11C7/1072 ,  H04L9/0816 ,  H04L9/0861 ,  H04L2209/12 ,  H04L2209/24

Abstract: A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers.

公开(公告)号：US20160261406A1

公开(公告)日：2016-09-08

申请号：US15079305

申请日：2016-03-24

Applicant: Intel Corporation

Inventor： Martin Dixon ,  Srinivas Chennupaty ,  Shay Gueron

IPC: H04L9/06

CPC classification number: H04L9/0631 ,  G06F9/30007 ,  H04L9/0637 ,  H04L2209/12

Abstract: A machine-readable medium may have stored thereon an instruction, which when executed by a machine causes the machine to perform a method. The method may include combining a first operand of the instruction and a second operand of the instruction to produce a result. The result may be encrypted using a key in accordance with an Advanced Encryption Standard (AES) algorithm to produce an encrypted result. The method may also include placing the encrypted result in a location of the first operand of the instruction.

公开(公告)号：US20160119131A1

公开(公告)日：2016-04-28

申请号：US14984686

申请日：2015-12-30

Applicant: Intel Corporation

Inventor： Gueron Shay ,  Wajdi K. Feghali ,  Vinodh Gopal ,  Raghunandan Makaram ,  Martin G. Dixon ,  Srinivas Chennupaty ,  Michael E. Kounavis

IPC: H04L9/06 ,  G06F12/08 ,  G11C7/10 ,  G06F12/14

CPC classification number: H04L9/0631 ,  G06F3/0623 ,  G06F3/0665 ,  G06F3/0689 ,  G06F9/30007 ,  G06F9/30036 ,  G06F9/30047 ,  G06F9/30145 ,  G06F9/30178 ,  G06F9/3802 ,  G06F9/3818 ,  G06F9/3887 ,  G06F9/3895 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/1408 ,  G06F21/602 ,  G06F2212/1052 ,  G06F2212/402 ,  G06F2212/452 ,  G06F2212/454 ,  G06F2212/602 ,  G11C7/1072 ,  H04L9/0816 ,  H04L9/0861 ,  H04L2209/12 ,  H04L2209/24

Abstract: A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers.

公开(公告)号：US20150178082A1

公开(公告)日：2015-06-25

申请号：US14562632

申请日：2014-12-05

Applicant: Intel Corporation

Inventor： Michael A. Julier ,  Jeffrey D. Gray ,  Srinivas Chennupaty ,  Sean P. Mirkes ,  Mark P. Seconi

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30145 ,  G06F7/06 ,  G06F9/30 ,  G06F9/3001 ,  G06F9/30021 ,  G06F9/30029 ,  G06F9/30036 ,  G06F9/30098 ,  G06F9/30109 ,  G06F9/3013 ,  G06F9/30167 ,  G06F9/3017 ,  G06F9/30185 ,  G06F9/30192 ,  G06F9/34 ,  G06F9/3802 ,  G06F9/3824 ,  G06F9/3853 ,  G06F9/3885 ,  G06F9/3887 ,  G06F12/0875 ,  G06F2212/452

Abstract: Method, apparatus, and program means for performing a string comparison operation. In one embodiment, an apparatus includes execution resources to execute a first instruction. In response to the first instruction, said execution resources store a result of a comparison between each data element of a first and second operand corresponding to a first and second text string, respectively.