公开(公告)号：US07463522B2

公开(公告)日：2008-12-09

申请号：US11745092

申请日：2007-05-07

申请人： Yingda Dong ,  Jeffrey W. Lutze ,  Shih-Chung Lee ,  Gerrit Jan Hemink ,  Ken Oowada

发明人： Yingda Dong ,  Jeffrey W. Lutze ,  Shih-Chung Lee ,  Gerrit Jan Hemink ,  Ken Oowada

IPC分类号： G11C16/00

CPC分类号： G11C8/08 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/3418 ,  G11C16/3427 ,  G11C2211/5621

摘要： Non-volatile storage in which program disturb is reduced by preventing source side boosting in selected NAND strings. A self-boosting mode which includes an isolation word line is used. A channel area of an inhibited NAND string is boosted on a source side of the isolation word line before the channel is boosted on a drain side of the isolation word line. Further, storage elements near the isolation word line are kept in a conducting state during the source side boosting so that the source side channel is connected to the drain side channel. In this way, in selected NAND strings, source side boosting can not occur and thus program disturb due to source side boosting can be prevented. After the source side boosting, the source side channel is isolated from the drain side channel, and drain side boosting is performed.

摘要翻译： 通过防止所选择的NAND串中的源极升压来减少编程干扰的非易失性存储。 使用包括隔离字线的自增强模式。 禁止的NAND串的通道区域在隔离字线的漏极侧的通道升压之前在隔离字线的源极侧被升压。 此外，在源侧升压期间，隔离字线附近的存储元件保持导通状态，使得源极侧沟道连接到漏极侧沟道。 以这种方式，在选择的NAND串中，不能发生源侧升压，因此可以防止由于源极侧升压而导致的编程干扰。 在源侧升压之后，源侧沟道与漏极侧沟道隔离，并且进行漏极侧升压。

公开(公告)号：US07460406B2

公开(公告)日：2008-12-02

申请号：US12023317

申请日：2008-01-31

申请人： Nima Mokhlesi ,  Jeffrey W. Lutze

发明人： Nima Mokhlesi ,  Jeffrey W. Lutze

IPC分类号： G11C11/34

CPC分类号： G11C16/28

摘要： The present invention presents a scheme for sensing memory cells. Selected memory cells are discharged through their channels to ground and then have a voltage level placed on the traditional source and another voltage level placed on the control gate, and allowing the cell bit line to charge up. The bit line of the memory cell will then charge up until the bit line voltage becomes sufficiently high to shut off any further cell conduction. The rise of the bit line voltage will occur at a rate and to a level dependent upon the data state of the cell, and the cell will then shut off when the bit line reaches a high enough level such that the body effect affected memory cell threshold is reached, at which point the current essentially shuts off. A particular embodiment performs multiple such sensing sub-operations, each with a different control gate voltage, but with multiple states being sensed in each operation by charging the previously discharged cells up through their source.

公开(公告)号：US20080291735A1

公开(公告)日：2008-11-27

申请号：US11753958

申请日：2007-05-25

申请人： Yingda Dong ,  Jeffrey W. Lutze ,  Dana Lee

发明人： Yingda Dong ,  Jeffrey W. Lutze ,  Dana Lee

IPC分类号： G11C11/34

CPC分类号： G11C16/12 ,  G11C16/0483 ,  G11C16/10

摘要： To program one or more non-volatile storage elements, a set of programming pulses are applied to at least one selected non-volatile storage element and one or more particular unselected non-volatile storage elements, for example, via a common word line. A boosting voltage is applied to other unselected non-volatile storage elements during the programming process in order to boost the channels of the unselected non-volatile storage elements so that programming will be inhibited. Each of the programming pulses has a first intermediate magnitude, a second intermediate magnitude and a third magnitude. In one embodiment, the first intermediate magnitude is similar to or the same as the boosting voltage. The second intermediate magnitude is greater than the first intermediate magnitude, but less then the third magnitude. Such an arrangement can reduce the effects of program disturb.

摘要翻译： 为了对一个或多个非易失性存储元件进行编程，例如通过公共字线将一组编程脉冲施加到至少一个选定的非易失性存储元件和一个或多个特定未选择的非易失性存储元件。 在编程过程期间将升压电压施加到其它未选择的非易失性存储元件，以便增强未选择的非易失性存储元件的通道，从而禁止编程。 每个编程脉冲具有第一中间幅度，第二中间幅度和第三幅度。 在一个实施例中，第一中间幅度与升压电压相似或相同。 第二中间幅度大于第一中间幅度，但小于第三幅度。 这样的布置可以减少节目干扰的影响。

公开(公告)号：US20080278999A1

公开(公告)日：2008-11-13

申请号：US12060487

申请日：2008-04-01

申请人： Yingda Dong ,  Jeffrey W. Lutze

发明人： Yingda Dong ,  Jeffrey W. Lutze

IPC分类号： G11C16/12

CPC分类号： G11C16/3418

摘要： Program disturb is reduced during programming of non-volatile storage by providing a boosting scheme in which isolation voltage are applied to two word lines to create a source side channel region on a source side of one isolation word line, an intermediate channel region between the isolation word lines and a drain side channel region on a drain side of the other isolation word line. Further, during a programming operation, the source and drain side channel regions are boosted early while the intermediate channel region is boosted later, when a program pulse is applied. This approach prevents charge leakage from the intermediate channel region to the source side, avoiding disturb of already programmed storage elements, while also allowing electrons to flow from the intermediate channel region to the drain side channel region, which makes the boosting of the intermediate channel region easier.

摘要翻译： 在非易失性存储器的编程期间通过提供一种升压方案来减少在非易失性存储器编程期间的编程干扰，其中隔离电压施加到两个字线以在一个隔离字线的源极侧产生源极侧沟道区，隔离层之间的中间沟道区 字线和另一个隔离字线的漏极侧的漏极侧沟道区。 此外，在编程操作期间，当施加编程脉冲时，源极和漏极侧通道区域早期被提升，而中间沟道区域稍后升压。 这种方法防止从中间通道区域到源极的电荷泄漏，避免已经编程的存储元件的干扰，同时还允许电子从中间沟道区域流到漏极侧沟道区域，这使得中间沟道区域的升压 更轻松。

公开(公告)号：US07450430B2

公开(公告)日：2008-11-11

申请号：US11618600

申请日：2006-12-29

申请人： Gerrit Jan Hemink ,  Yingda Dong ,  Jeffrey W. Lutze ,  Dana Lee

发明人： Gerrit Jan Hemink ,  Yingda Dong ,  Jeffrey W. Lutze ,  Dana Lee

IPC分类号： G11C16/06

CPC分类号： G11C16/3418 ,  G11C7/1048 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/3427

摘要： Unselected groups of non-volatile storage elements are boosted during programming to reduce or eliminate program disturb for targeted, but unselected memory cells connected to a selected word line. Prior to applying a program voltage to the selected word line and boosting the unselected groups, the unselected groups are pre-charged to further reduce or eliminate program disturb by providing a larger boosted potential for the unselected groups. During pre-charging, one or more pre-charge enable signals are provided at different voltages for particular non-volatile storage elements.

摘要翻译： 在编程期间，未选择的非易失性存储元件组被提升以减少或消除连接到所选字线的目标但未选择的存储器单元的程序干扰。 在将程序电压施加到所选择的字线并升高未选择的组之前，未选择的组被预先充电，以通过为未选择的组提供更大的增强电位来进一步减少或消除程序干扰。 在预充电期间，对于特定的非易失性存储元件，以不同的电压提供一个或多个预充电使能信号。

公开(公告)号：US20080159003A1

公开(公告)日：2008-07-03

申请号：US11618594

申请日：2006-12-29

申请人： Yingda Dong ,  Jeffrey W. Lutze ,  Dana Lee ,  Gerrit Jan Hemink

发明人： Yingda Dong ,  Jeffrey W. Lutze ,  Dana Lee ,  Gerrit Jan Hemink

IPC分类号： G11C16/06

CPC分类号： G11C16/0483 ,  G11C7/1048 ,  G11C11/5628 ,  G11C16/3418 ,  G11C16/3427

摘要： Unselected groups of non-volatile storage elements are boosted during programming to reduce or eliminate program disturb for targeted, but unselected memory cells connected to a selected word line. Prior to applying a program voltage to the selected word line and boosting the unselected groups, the unselected groups are pre-charged to further reduce or eliminate program disturb by providing a larger boosted potential for the unselected groups. During pre-charging, one or more pre-charge enable signals are provided at higher voltages for certain memory cells that may have undergone partial programming.

摘要翻译： 在编程期间，未选择的非易失性存储元件组被提升以减少或消除连接到所选字线的目标但未选择的存储器单元的程序干扰。 在将程序电压施加到所选择的字线并升高未选择的组之前，未选择的组被预先充电，以通过为未选择的组提供更大的增强电位来进一步减少或消除程序干扰。 在预充电期间，对于可能已经经过部分编程的某些存储器单元，在较高电压下提供一个或多个预充电使能信号。

公开(公告)号：US20080158991A1

公开(公告)日：2008-07-03

申请号：US11618606

申请日：2006-12-29

申请人： Gerrit Jan Hemink ,  Yingda Dong ,  Jeffrey W. Lutze ,  Dana Lee

发明人： Gerrit Jan Hemink ,  Yingda Dong ,  Jeffrey W. Lutze ,  Dana Lee

IPC分类号： G11C7/00 ,  G11C7/06 ,  G11C16/06

CPC分类号： G11C16/3418 ,  G11C7/1048 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3427

摘要： Unselected groups of non-volatile storage elements are boosted during programming to reduce or eliminate program disturb for targeted, but unselected memory cells connected to a selected word line. Prior to applying a program voltage to the selected word line and boosting the unselected groups, the unselected groups are pre-charged to further reduce or eliminate program disturb by providing a larger boosted potential for the unselected groups. During pre-charging, one or more pre-charge enable signals are provided at different voltages for particular non-volatile storage elements.

摘要翻译： 在编程期间，未选择的非易失性存储元件组被提升以减少或消除连接到所选字线的目标但未选择的存储器单元的程序干扰。 在将程序电压施加到所选择的字线并升高未选择的组之前，未选择的组被预先充电，以通过为未选择的组提供更大的增强电位来进一步减少或消除程序干扰。 在预充电期间，对于特定的非易失性存储元件，以不同的电压提供一个或多个预充电使能信号。

公开(公告)号：US07349264B2

公开(公告)日：2008-03-25

申请号：US11321996

申请日：2005-12-28

申请人： Nima Mokhlesi ,  Jeffrey W. Lutze

发明人： Nima Mokhlesi ,  Jeffrey W. Lutze

IPC分类号： G11C11/34

CPC分类号： G11C16/28

摘要： The present invention presents a scheme for sensing memory cells. Selected memory cells are discharged through their channels to ground and then have a voltage level placed on the traditional source and another voltage level placed on the control gate, and allowing the cell bit line to charge up. The bit line of the memory cell will then charge up until the bit line voltage becomes sufficiently high to shut off any further cell conduction. The rise of the bit line voltage will occur at a rate and to a level dependent upon the data state of the cell, and the cell will then shut off when the bit line reaches a high enough level such that the body effect affected memory cell threshold is reached, at which point the current essentially shuts off. A particular embodiment performs multiple such sensing sub-operations, each with a different control gate voltage, but with multiple states being sensed in each operation by charging the previously discharged cells up through their source.

摘要翻译： 本发明提供了一种用于感测存储器单元的方案。 所选择的存储单元通过其通道放电到地，然后将电压电平放置在传统源上，并将另一个电压电平放置在控制栅上，并允许单元位线充电。 存储单元的位线然后将充电直到位线电压变得足够高以截止任何进一步的单元导通。 位线电压的升高将以一定的速率发生，并且取决于单元的数据状态，并且当位线达到足够高的电平时，单元将关闭，使得体效应影响存储单元阈值 到达目前，当前基本上关闭。 特定实施例执行多个这样的感测子操作，每个具有不同的控制栅极电压，但是在每个操作中通过对先前放电的单元通过其源极充电来感测多个状态。

公开(公告)号：US07230854B2

公开(公告)日：2007-06-12

申请号：US11194439

申请日：2005-08-01

申请人： Jun Wan ,  Jeffrey W. Lutze

发明人： Jun Wan ,  Jeffrey W. Lutze

IPC分类号： G11C11/34 ,  G11C7/00

CPC分类号： G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3454 ,  G11C16/3459 ,  G11C2211/5621

摘要： The maximum allowable number of voltage programming pulses to program memory elements of a non-volatile memory device is adjusted to account for changes in the memory elements which occur over time. Programming pulses are applied until the threshold voltage of one or more memory elements reaches a certain verify level, after which a defined maximum number of additional pulses may be applied to other memory elements to allow them to also reach associated target threshold voltage levels. The technique enforces a maximum allowable number of programming pulses that can change over time as the memory is cycled.

公开(公告)号：US07170788B1

公开(公告)日：2007-01-30

申请号：US11223273

申请日：2005-09-09

申请人： Jun Wan ,  Jeffrey W. Lutze

发明人： Jun Wan ,  Jeffrey W. Lutze

IPC分类号： G11C11/34 ,  G11C16/06

CPC分类号： G11C16/3418 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3427 ,  G11C2211/5648

摘要： A non-volatile memory is programmed in a manner which reduces the incidence of program disturb for inhibited memory elements which undergo boosting to reduce program disturb, but which experience reduced boosting benefits due to their word line location. To achieve this result, a word line sequence in which the memory elements are programmed is adjusted so that higher word lines are programmed first, out of sequence relative to the remaining word lines. Additionally, self-boosting can be used for the higher word lines, while erased area self-boosting or a variant can be used for the remaining word lines. Furthermore, pre-charging of the channel of the inhibited memory elements may be employed prior to the self boosting, for the non-volatile storage elements which are programmed after those associated with the first word line.

摘要翻译： 非易失性存储器被编程为减少对经过增强的抑制存储器元件的编程干扰的发生率以减少编程干扰的方式，但是哪些经验减少了由于其字线位置而引起的益处。 为了实现该结果，调整存储器元件被编程的字线序列，使得较高的字线首先被编程，而不是相对于剩余的字线的顺序。 另外，自增强可以用于较高的字线，而擦除区域自增强或变体可用于剩余的字线。 此外，对于在与第一字线相关联的那些之后编程的非易失性存储元件，可以在自增强之前采用禁止的存储器元件的通道的预充电。