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公开(公告)号：US20240312533A1
公开(公告)日：2024-09-19
申请号：US18677727
申请日：2024-05-29
申请人： Kioxia Corporation
发明人： Yoshihisa KOJIMA
IPC分类号： G11C16/32 , G11C7/04 , G11C11/56 , G11C16/04 , G11C16/08 , G11C16/10 , G11C16/26 , G11C16/34
CPC分类号： G11C16/32 , G11C7/04 , G11C11/5628 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/26 , G11C16/3495 , G11C2211/5648
摘要： A memory system includes a nonvolatile memory configured to execute one of a plurality of read operations, including a first read operation and a second read operation, and a memory controller configured to issue a read command to the nonvolatile memory to cause the nonvolatile memory to execute one of the plurality of read operations. The memory controller is configured to receive a read request, estimate a reliability level of a result of a read operation to be executed by the nonvolatile memory to read data from a physical address specified in the read request, select one of the first and second read operations to be executed first in a read sequence corresponding to the read request by the nonvolatile memory based on the estimated reliability level, and instruct the nonvolatile memory to execute the selected read operation.
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公开(公告)号：US20230352101A1
公开(公告)日：2023-11-02
申请号：US18219083
申请日：2023-07-06
申请人： Silicon Motion, Inc.
发明人： Tsung-Chieh Yang
IPC分类号： G11C16/26 , G11C11/56 , G11C16/04 , G06F11/10 , G11C29/52 , G06F3/06 , G11C16/34 , H03M13/15
CPC分类号： G11C16/26 , G11C11/5642 , G11C16/0483 , G06F11/1068 , G11C29/52 , G06F11/1072 , G06F3/0619 , G06F3/064 , G06F3/0659 , G06F3/0679 , G11C16/3427 , H03M13/152 , G11C2211/5644 , G11C2211/5648 , G11C16/0475
摘要： A method for reading data stored in a flash memory includes at least the following steps: controlling the flash memory to perform a plurality of read operations upon a plurality of memory cells included in the flash memory; obtaining a plurality of bit sequences read from the memory cells, respectively, wherein the read operations read bits of a predetermined bit order from the memory cells by utilizing different control gate voltage settings; and determining readout information of the memory cells according to binary digit distribution characteristics of the bit sequences.
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3.发明申请公开(公告)号：US20190172544A1
公开(公告)日：2019-06-06
申请号：US15996485
申请日：2018-06-03
发明人： SEUNG-BUM KIM , DEOK-WOO LEE , DONG-HUN KWAK
CPC分类号： G11C16/3445 , G11C11/5628 , G11C11/5635 , G11C11/5671 , G11C16/0483 , G11C16/10 , G11C16/14 , G11C16/30 , G11C16/3427 , G11C2211/5648 , H01L27/1157 , H01L27/11582
摘要： A non-volatile memory device includes multiple word lines, and a voltage generator. Some of the word lines correspond to a deterioration area. The voltage generator is configured to generate a program voltage provided to multiple memory cells through the word lines. Control logic implemented by the non-volatile memory device is configured to control a program operation and an erase operation on the word lines. The deterioration area includes word lines of a first group and word lines of a second group. The control logic is configured to control a program sequence so that each of the word lines of the second group is programmed after an adjacent word line of the first group is programmed, and to control a distribution so that a threshold voltage level corresponding to an erase state of each of the word lines of the first group is higher than a threshold voltage level corresponding to an erase state of each of the word lines of the second group.
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公开(公告)号：US20190074057A1
公开(公告)日：2019-03-07
申请号：US16125601
申请日：2018-09-07
发明人： NOBORU SHIBATA , Tomoharu Tanaka
CPC分类号： G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/10 , G11C16/12 , G11C16/3454 , G11C16/3459 , G11C2211/5621 , G11C2211/5648
摘要： A memory cell array is configured to have a plurality of memory cells arranged in a matrix, each of the memory cells being connected to a word line and a bit line and being capable of storing n values (n is a natural number equal to or larger than 3). A control circuit controls the potentials of the word line and bit line according to input data and writes data into a memory cell. The control circuit writes data into the memory cell to a k-valued threshold voltage (k
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公开(公告)号：US09940031B2
公开(公告)日：2018-04-10
申请号：US15462300
申请日：2017-03-17
发明人： Takuya Futatsuyama
CPC分类号： G06F3/061 , G06F3/0619 , G06F3/0652 , G06F3/0656 , G06F3/0679 , G06F3/0688 , G11C11/5628 , G11C16/0408 , G11C16/045 , G11C16/0483 , G11C16/10 , G11C16/3418 , G11C2211/5648
摘要： A nonvolatile semiconductor memory device comprises a cell unit including a first and a second selection gate transistor and a memory string provided between the first and second selection gate transistors and composed of a plurality of serially connected electrically erasable programmable memory cells operative to store effective data; and a data write circuit operative to write data into the memory cell, wherein the number of program stages for at least one of memory cells on both ends of the memory string is lower than the number of program stages for other memory cells, and the data write circuit executes the first stage program to the memory cell having the number of program stages lower than the number of program stages for the other memory cells after the first stage program to the other memory cells.
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公开(公告)号：US20180096722A1
公开(公告)日：2018-04-05
申请号：US15831718
申请日：2017-12-05
CPC分类号： G11C11/5628 , G11C16/0408 , G11C16/0458 , G11C16/10 , G11C16/3418 , G11C16/3427 , G11C2211/562 , G11C2211/5622 , G11C2211/5642 , G11C2211/5648
摘要： Memory devices include control logic configured to set a first start program voltage and a first stop program voltage, to load actual first data for cells to be programmed to a level greater than or equal to a first level, and to load inhibit data for cells to be programmed to a level less than a second level. After programming the cells to be programmed to the level greater than or equal to the first level, the control logic is further configured to set a second start program voltage and a second stop program voltage, to load inhibit data for the cells programmed to the level greater than or equal to the first level, and to load actual second data for the cells to be programmed to the level less than the second level, wherein the first level is one level higher than the second level.
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公开(公告)号：US20180061498A1
公开(公告)日：2018-03-01
申请号：US15556680
申请日：2015-06-19
申请人： Hitachi, Ltd.
发明人： Yohei HAZAMA , Junji OGAWA , Kenta NINOSE
CPC分类号： G11C16/26 , G06F3/067 , G06F3/0688 , G06F11/1048 , G06F11/1068 , G06F11/1076 , G06F12/16 , G11C11/5642 , G11C16/349 , G11C2211/5648
摘要： A flash memory controller is configured to hold a read pattern defining an order of selection of read options specifying a parameter value for a read from the flash memory chip. The flash memory controller is configured to execute error correction on data read from the flash memory chip in accordance with the read command. The flash memory controller is configured to designate a next read option specified in the read pattern to read the data from the flash memory chip in a case where all errors in the read data are not corrected by the error correction.
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公开(公告)号：US09891988B2
公开(公告)日：2018-02-13
申请号：US15467348
申请日：2017-03-23
发明人： Tobias Blaettler , Thomas Mittelholzer , Nikolaos Papandreou , Thomas Parnell , Charalampos Pozidis , Milos Stanisavljevic
CPC分类号： G06F11/1048 , G06F11/1072 , G11C7/1006 , G11C11/56 , G11C11/5628 , G11C16/10 , G11C2211/5648
摘要： A device for storing data in a plurality of multi-level cell memory chips. The device includes a scrambling unit to generate a plurality of candidate scrambled sequences of data by performing a plurality of scrambling operations on a sequence of data to be stored, a calculation unit to calculate a cost function for each of the plurality of candidate scrambled sequences of data, the result of each cost function being indicative of a balancing degree of subsequences of a candidate scrambled sequence, when the subsequences of the candidate scrambled sequence are written to the plurality of multi-level cell memory chips, a selection unit to select one of the candidate scrambled sequences of data based on the results of the cost functions, and a storing unit to store the selected candidate scrambled sequence of data in the multi-level cell memory chips by storing the subsequences across the multi-level memory chips.
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公开(公告)号：US09881681B2
公开(公告)日：2018-01-30
申请号：US15251798
申请日：2016-08-30
发明人： Noboru Shibata , Tomoharu Tanaka
CPC分类号： G11C16/3427 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/10 , G11C16/12 , G11C16/3459 , G11C2211/5621 , G11C2211/5646 , G11C2211/5648 , G11C2216/14
摘要： Data storage circuits are connected to the bit lines in a one-to-one correspondence. A write circuit writes the data on a first page into a plurality of 5 first memory cells selected simultaneously by a word line. Thereafter, the write circuit writes the data on a second page into the plurality of first memory cell. Then, the write circuit writes the data on the first and second pages into second memory cells adjoining 10 the first memory cells in the bit line direction.
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10.发明授权公开(公告)号：US09747973B2
公开(公告)日：2017-08-29
申请号：US14992285
申请日：2016-01-11
发明人： Ming-Hsuan Lee , Sen-Ming Chuang , Jen-Cheng Liu
CPC分类号： G11C11/5628 , G11C16/105 , G11C16/225 , G11C16/30 , G11C2211/5648
摘要： A data writing method for a solid state storage device includes following steps. A step (a) is performed to judge whether a shutdown command is issued from a host. In a step (b), if the solid state storage device confirms that the shutdown command is not issued from the host, plural program procedures are performed. Consequently, plural write data in a buffer are stored to a triple-level cell flash memory according to a program order. In a step (c), if the solid state storage device confirms that the shutdown command is issued from the host, plural redundant data are added to the plural write data, the write data are stored into the buffer, and the plural program procedures are performed. Consequently, the plural write data in the buffer are stored to the triple-level cell flash memory according to the program order.
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