公开(公告)号：US20080209437A1

公开(公告)日：2008-08-28

申请号：US12118958

申请日：2008-05-12

申请人： Philip G. Emma

发明人： Philip G. Emma

IPC分类号： G06F9/46

CPC分类号： G06F9/3885 ,  G06F9/3851 ,  G06F9/3867

摘要： A uniprocessor that can run multiple threads (programs) simultaneously is achieved by use of a plurality of low-frequency minicore processors, each minicore for receiving a respective thread from a high-frequency cache and processing the thread. A superscalar processor may be used in conjunction with the uniprocessor to process threads requiring high throughput.

摘要翻译： 可以通过使用多个低频小型处理器来实现可同时运行多个线程（程序）的单处理器，每个微型处理器用于从高频缓存接收相应的线程并处理线程。 超标量处理器可以与单处理器一起使用以处理需要高吞吐量的线程。

公开(公告)号：US20080046684A1

公开(公告)日：2008-02-21

申请号：US11465247

申请日：2006-08-17

申请人： Philip G. Emma

发明人： Philip G. Emma

IPC分类号： G06F15/00

CPC分类号： G06F9/3885 ,  G06F9/3851 ,  G06F9/3867

摘要： A uniprocessor that can run multiple threads (programs) simultaneously is achieved by use of a plurality of low-frequency minicore processors, each minicore for receiving a respective thread from a high-frequency cache and processing the thread. A superscalar processor may be used in conjunction with the uniprocessor to process threads requiring high throughput.

公开(公告)号：US07015570B2

公开(公告)日：2006-03-21

申请号：US10314574

申请日：2002-12-09

申请人： Philip G. Emma ,  Arthur R. Zingher

发明人： Philip G. Emma ,  Arthur R. Zingher

IPC分类号： H01L23/48 ,  H01L29/786 ,  G02F1/136 ,  G02F1/1343 ,  G09F9/35

CPC分类号： H01L23/5386 ,  H01L2224/48137 ,  H01L2224/48472 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/147 ,  H05K1/148 ,  H05K3/222 ,  H05K3/361 ,  H01L2924/00

摘要： A multi-connect substrate, module including the substrate and an Integrated Circuit (IC) chip packaged in the module. The multi-connect substrate includes a multilayered substrate with at least one edge terminal array and one inboard terminal array on one face. An exterior terminal array is located on an opposite face. Signal wires pass through the multilayered substrate, connecting edge terminals to inboard terminals and inboard terminals with a exterior array terminals.

摘要翻译： 一种多连接衬底，包括衬底的模块和封装在模块中的集成电路（IC）芯片。 多连接衬底包括具有至少一个边缘端子阵列和一个面上的一个内部端子阵列的多层衬底。 外部端子阵列位于相对的面上。 信号线通过多层基板，将边缘端子连接到内部端子和具有外部阵列端子的内部端子。

公开(公告)号：US06829413B2

公开(公告)日：2004-12-07

申请号：US10307951

申请日：2002-12-02

申请人： Cameron J. Brooks ,  Philip G. Emma ,  Casimer M. DeCusatis ,  Lawrence Jacobowitz ,  John U. Knickerbocker

发明人： Cameron J. Brooks ,  Philip G. Emma ,  Casimer M. DeCusatis ,  Lawrence Jacobowitz ,  John U. Knickerbocker

IPC分类号： G02B626

CPC分类号： G02B6/3636 ,  G02B6/3608 ,  G02B6/3652 ,  G02B6/3676 ,  G02B6/43

摘要： A ferrule-less optical backplane connector assembly includes a substrate having at least a pair of optical guide receiving structures formed therein, the pair of optical guide receiving structures further being formed at substantially a right angle with respect to one another so as to guide a corresponding first and second optical guide into optical alignment with one another.

摘要翻译： 一种无套圈的光背板连接器组件包括具有形成在其中的至少一对光导接收结构的基板，所述一对光导接收结构进一步相对于彼此基本成直角地形成，以便引导相应的 第一和第二光导件彼此光学对准。

公开(公告)号：US5353421A

公开(公告)日：1994-10-04

申请号：US91416

申请日：1993-07-13

申请人： Philip G. Emma ,  Joshua W. Knight ,  James H. Po merene ,  Thomas R. Puzak ,  Rudolph N. Rechtschaffen ,  James R. Robinson

发明人： Philip G. Emma ,  Joshua W. Knight ,  James H. Po merene ,  Thomas R. Puzak ,  Rudolph N. Rechtschaffen ,  James R. Robinson

IPC分类号： G06F9/38

CPC分类号： G06F9/3806 ,  G06F9/3848

摘要： A multi-prediction branch prediction mechanism predicts each conditional branch at least twice, first during the instruction-fetch phase of the pipeline and then again during the decode phase of the pipeline. The mechanism uses at least two different branch prediction mechanisms, each a separate and independent mechanism from the other. A set of rules are used to resolve those instances as to when the predictions differ.

摘要翻译： 多预测分支预测机制首先在流水线的指令获取阶段期间至少预测每个条件分支，然后再次在流水线的解码阶段期间。 该机制使用至少两个不同的分支预测机制，每个分离机制与另一个独立的机制相互独立。 使用一组规则来解决这些实例关于预测不同的情况。

公开(公告)号：US5155831A

公开(公告)日：1992-10-13

申请号：US342493

申请日：1989-04-24

申请人： Philip G. Emma ,  Joshua W. Knight ,  James H. Pomerene ,  Rudolph N. Rechtschaffen ,  Frank J. Sparacio

发明人： Philip G. Emma ,  Joshua W. Knight ,  James H. Pomerene ,  Rudolph N. Rechtschaffen ,  Frank J. Sparacio

IPC分类号： G06F7/78 ,  G06F12/08 ,  G06F15/16 ,  G06F15/177

CPC分类号： G06F7/785 ,  G06F12/0804 ,  G06F12/0828

摘要： A fast queue mechanism is provided which keeps a queue of changes (i.e. store actions) issued by each processor, which queue is accessible by all processors. When any processor issues a store action to a line of memory in the queue, the old data is overwritten with the new data. If the queue does not currently have a corresponding entry, a new entry is activated. Room for the new entry is made by selecting some existing entry, either the oldest or the least recently used, to be removed. An entry that is to be removed is first used to update the line corresponding to it in main memory. After the changes held in the entry to be removed are applied to the old value of the line (from main memory) and the updated value is put back into main memory, the entry in the queue is removed by marking it "empty". When a processor accesses a line of data not in its cache, a cache miss occurs and it is necessary to fetch the line from main memory. Such fetches are monitored by the queue mechanism to see if it is holding changes to the line being fetched. If so, the changes are applied to the line coming from main memory before the line is sent to the requesting processor. After a new entry is made in the queue mechanism, other store actions to the same entry by any processor may occur and usually a number of store actions will occur to the entry before it is removed to make room for another.