公开(公告)号：US20110193605A1

公开(公告)日：2011-08-11

申请号：US12703249

申请日：2010-02-10

Applicant: Bin Zhao

Inventor： Bin Zhao

IPC: H03K3/017

CPC classification number: H05B33/0818 ,  G06F1/025 ,  Y02B20/346

Abstract: A pulse width modulation (PWM) signal generator generates a PWM signal with an adjustable PWM duty based on a programmable or otherwise adjustable value. In response to a change or update to this value, the PWM signal generator initiates a duty transition process that generates a series of groups of PWM cycles that gradually transition from the original duty to the new duty. Each group includes a corresponding set of a predetermined number of PWM cycles that is repeated one or more times over a predetermined duration for the group. Each set has a certain proportion of PWM cycles having the new duty to PWM cycles having the original duty, whereby the proportion increases for each successive group of the series. This gradual transition in the PWM signal from the original duty to the new duty effectively provides an effective higher duty resolution for the PWM signal generator during the duty transition.

Abstract translation: 脉冲宽度调制（PWM）信号发生器基于可编程或其他可调整的值产生具有可调PWM占空比的PWM信号。 响应于该值的更改或更新，PWM信号发生器启动占空比转换过程，该过程产生逐渐从原始占空比转换到新占空比的一系列PWM周期。 每个组包括在该组的预定持续时间内重复一次或多次的预定数量的PWM周期的相应组。 每组具有一定比例的PWM周期，其具有具有原始占空比的PWM周期的新占空比，由此该系列的每个连续组的比例增加。 在占空比过渡期间，PWM信号从原始占空比到新占空比的逐渐转换有效地为PWM信号发生器提供了更高的占空比分辨率。

公开(公告)号：US20110121761A1

公开(公告)日：2011-05-26

申请号：US12625818

申请日：2009-11-25

Applicant: Bin Zhao

Inventor： Bin Zhao

IPC: H05B43/00 ,  H03L7/07

CPC classification number: H05B33/0818 ,  H05B33/0827 ,  H05B33/0848

Abstract: A pulse width modulation (PWM) signal generator generates multiple output PWM signals from an input PWM signal. The output PWM signals are synchronized to synchronization events. Each output PWM signal has a duty ratio substantially equal to the duty ratio of the input PWM signal, and each output PWM signal has a fixed phase-shift in relation to the other output PWM signals. The PWM signal generator samples an input PWM cycle to determine sample parameters representative of its duty ratio. The sample parameters are then used to generate a corresponding output PWM cycle for each of the output PWM signals. In response to a synchronization event, the PWM signal generator prematurely terminates the current PWM cycle and initiates the next PWM cycle while ensuring that the portion of the current output PWM cycle completed by the leading output PWM signal up to the point of the premature termination is replicated for the corresponding output PWM cycles of the other non-leading output PWM signals.

Abstract translation: 脉宽调制（PWM）信号发生器从输入PWM信号产生多个输出PWM信号。 输出PWM信号与同步事件同步。 每个输出PWM信号的占空比基本上等于输入PWM信号的占空比，并且每个输出PWM信号相对于其它输出PWM信号具有固定的相移。 PWM信号发生器对输入PWM周期进行采样，以确定代表其占空比的采样参数。 然后使用采样参数为每个输出PWM信号产生相应的输出PWM周期。 响应于同步事件，PWM信号发生器过早地终止当前的PWM周期并启动下一个PWM周期，同时确保由引导输出PWM信号完成的电流输出PWM周期的部分直到提前终止点为止 复制其他非前置输出PWM信号的相应输出PWM周期。

公开(公告)号：US20110012519A1

公开(公告)日：2011-01-20

申请号：US12504841

申请日：2009-07-17

Applicant: Bin Zhao

Inventor： Bin Zhao

IPC: H05B37/02 ,  H03M1/10

CPC classification number: H03M1/1235 ,  H05B33/0827

Abstract: An analog-to-digital converter (ADC) implements non-uniform conversion accuracy so as to allow for high conversion accuracy for a select narrower input range while also accommodating a wider overall input range and requiring fewer conversion bits compared to conventional ADCs. The ADC includes an ADC core that receives an input signal and outputs a first digital value having a first number of bits, the first digital value based on the input signal and an accuracy configuration of the ADC core. The ADC also includes an encoder to generate a second digital value have a second number of bits, greater than the first number of bits, based on the first digital value and the accuracy configuration of the ADC core. The ADC further includes an accuracy controller to adjust the accuracy configuration of the ADC core based on a relationship between the first digital value and at least one threshold.

Abstract translation: 模数转换器（ADC）实现了非均匀的转换精度，以便在选择更窄的输入范围内实现高转换精度，同时还适应更宽的整体输入范围，与传统ADC相比需要较少的转换位。 ADC包括ADC内核，其接收输入信号并输出​​具有第一数量位的第一数字值，基于输入信号的第一数字值和ADC内核的精度配置。 ADC还包括一个编码器，用于根据第一数字值和ADC内核的精度配置，产生具有大于第一位数的第二位数的第二数字值。 ADC还包括精度控制器，用于基于第一数字值与至少一个阈值之间的关系来调整ADC内核的精度配置。

公开(公告)号：US20100191881A1

公开(公告)日：2010-07-29

申请号：US12358437

申请日：2009-01-23

Applicant: Marcin P. Tauter ,  Christine Teresa Munson ,  Lin Shi ,  Bin Zhao ,  Peter A. Cryer ,  George D. Watt ,  Vasken Torossian

Inventor： Marcin P. Tauter ,  Christine Teresa Munson ,  Lin Shi ,  Bin Zhao ,  Peter A. Cryer ,  George D. Watt ,  Vasken Torossian

IPC: G06F13/00

CPC classification number: G06Q10/06

Abstract: A method for reserving and provisioning IT resources comprises receiving, from a user, a request to reserve a desired configuration of IT resources. The desired configuration comprises one or more desired technical specifications and a desired reservation time having a start time and an end time. The method further comprises accessing an IT resource database to determine one or more of a plurality of resource pools that the user has access to. The one or more resource pools are consulted to determine if one or more IT resources matching the desired configuration are available. If the one or more IT resources matching the desired configuration are available, the one or more IT resources are reserved for the user and provided to the user at the start time.

Abstract translation: 用于保留和配置IT资源的方法包括从用户接收保留IT资源的期望配置的请求。 期望的配置包括一个或多个期望的技术规范和具有开始时间和结束时间的期望的预留时间。 该方法还包括访问IT资源数据库以确定用户具有访问权限的多个资源池中的一个或多个。 咨询一个或多个资源池以确定是否有可用与所需配置匹配的一个或多个IT资源。 如果符合所需配置的一个或多个IT资源可用，则一个或多个IT资源被保留给用户并且在开始时提供给用户。

公开(公告)号：US20100156315A1

公开(公告)日：2010-06-24

申请号：US12340985

申请日：2008-12-22

Applicant: Bin Zhao ,  Jack W. Cornish ,  Brian B. Horng ,  Andrew M. Kameya ,  Jan Krellner ,  Kenneth C. Kwok ,  Victor K. Lee ,  Weizhuang W. Xin

Inventor： Bin Zhao ,  Jack W. Cornish ,  Brian B. Horng ,  Andrew M. Kameya ,  Jan Krellner ,  Kenneth C. Kwok ,  Victor K. Lee ,  Weizhuang W. Xin

IPC: H05B41/36

CPC classification number: H05B33/0818 ,  H05B33/0827 ,  H05B33/0851

Abstract: Power management in a light emitting diode (LED) system having a plurality of LED strings is disclosed. A voltage source provides an output voltage to drive a plurality of LED strings. An LED driver implements a feedback mechanism to monitor the tail voltages of the active LED strings to identify the minimum tail voltage and adjust the output voltage of the voltage source based on the lowest tail voltage. A loop calibration module of the LED driver calibrates the feedback mechanism of the LED driver based on a relationship between a digital code value used to generate a particular output voltage and another digital code value generated based on the minimum tail voltage resulting from the particular output voltage.

Abstract translation: 公开了具有多个LED串的发光二极管（LED）系统中的电源管理。 电压源提供输出电压以驱动多个LED串。 LED驱动器实现反馈机制来监测有源LED串的尾部电压以识别最小尾电压，并且基于最低的尾部电压来调节电压源的输出电压。 LED驱动器的回路校准模块基于用于产生特定输出电压的数字代码值与基于由特定输出电压产生的最小尾部电压产生的另一数字代码值之间的关系来校准LED驱动器的反馈机制 。

公开(公告)号：US20100026203A1

公开(公告)日：2010-02-04

申请号：US12183492

申请日：2008-07-31

Applicant: Bin Zhao ,  Jack W. Cornish ,  Brian B. Horng ,  Andrew M. Kameya ,  Jan Krellner ,  Kenneth C. Kwok ,  Victor K. Lee ,  Weizhuang W. Xin

Inventor： Bin Zhao ,  Jack W. Cornish ,  Brian B. Horng ,  Andrew M. Kameya ,  Jan Krellner ,  Kenneth C. Kwok ,  Victor K. Lee ,  Weizhuang W. Xin

IPC: H05B33/00

CPC classification number: H05B33/0815 ,  H05B33/0827 ,  H05B33/086

Abstract: Disclosed are example techniques for frame-based power management in a light emitting diode (LED) system having a plurality of LED strings. A voltage source provides an output voltage to drive the LED strings. An LED driver generates a frame timing reference representative of the frame rate or display timing of a series of image frames to be displayed via the LED system. An update reference is generated from the frame timing reference. The LED driver monitors one or more operating parameters of the LED system. In response to update triggers marked by the update reference, the LED driver adjusts the output voltage of the voltage source based on the status of each of the one or more monitored operating parameters (either from the previous update period or determined in response to the update trigger), thereby synchronizing the updating of the output voltage to the frame rate (or a virtual approximation of the frame rate) of the video being displayed.

Abstract translation: 公开了具有多个LED串的发光二极管（LED）系统中用于基于帧的电源管理的示例技术。 电压源提供输出电压来驱动LED串。 LED驱动器生成表示要通过LED系统显示的一系列图像帧的帧速率或显示定时的帧定时参考。 从帧定时参考生成更新参考。 LED驱动器监视LED系统的一个或多个操作参数。 响应于由更新参考标记的更新触发器，LED驱动器基于一个或多个监视的操作参数中的每一个的状态来调节电压源的输出电压（从先前的更新周期或响应于更新确定） 触发），从而将输出电压的更新同步于正在显示的视频的帧速率（或帧速率的虚拟近似）。

公开(公告)号：US20080018358A1

公开(公告)日：2008-01-24

申请号：US11473351

申请日：2006-06-22

Applicant: Bin Zhao

Inventor： Bin Zhao

IPC: H03K19/003

CPC classification number: H03K19/018557 ,  H03K17/063 ,  H03K17/102 ,  H03K17/687

Abstract: A semiconductor network is interposed between first and second multiple-port interfaces each having high-voltage, intermediate-voltage and ground ports to form a switch assembly. The assembly includes a primary switch circuit, a support network, internal and external-port circuits and internal and external-port control circuits. The primary switch circuit is coupled to high-voltage ports of the multiple-port interfaces and to the support network. The internal and external-port circuits are coupled to intermediate-voltage ports of the multiple-port interfaces, the internal and external-port control circuits and the support network. The internal-port control circuit is coupled to the internal-port circuit, the support network and a ground port of a first multiple-port interface. The external-port control circuit is coupled to the external-port circuit, the support network and a ground port of the second multiple-port interface. The assembly has a low-leakage current in both open and closed states when exposed to a range of high voltages.

Abstract translation: 半导体网络介于第一和第二多端口接口之间，每个端口具有高电压，中间电压和接地端口以形成开关组件。 组件包括主开关电路，支撑网络，内部和外部端口电路以及内部和外部端口控制电路。 主开关电路耦合到多端口接口的高压端口和支持网络。 内部和外部端口电路耦合到多端口接口的中压端口，内部和外部端口控制电路和支持网络。 内部端口控制电路耦合到内部端口电路，支持网络和第一多端口接口的接地端口。 外部端口控制电路耦合到外部端口电路，支持网络和第二多端口接口的接地端口。 当暴露于一定范围的高电压时，组件在打开和关闭状态都具有低漏电流。

公开(公告)号：US20080003626A1

公开(公告)日：2008-01-03

申请号：US11724983

申请日：2007-03-16

Applicant: Joleen White ,  Lisa Flay ,  Erik Foehr ,  Gary Taniguchi ,  William Prince ,  Bin Zhao

Inventor： Joleen White ,  Lisa Flay ,  Erik Foehr ,  Gary Taniguchi ,  William Prince ,  Bin Zhao

IPC: G01N33/536

CPC classification number: G01N33/6854 ,  G01N33/573 ,  G01N2333/924

Abstract: The present invention relates to methods for screening body fluids or tissues for antibodies, including neutralizing and isotype-specific antibodies, against lysosomal enzymes administered as part of enzyme replacement therapy.

Abstract translation: 本发明涉及用于针对作为酶替代疗法的一部分而施用的溶酶体酶筛选用于抗体的体液或组织的方法，包括中和和同种型特异性抗体。

公开(公告)号：US07254268B2

公开(公告)日：2007-08-07

申请号：US10123019

申请日：2002-04-11

Applicant: Bin Zhao ,  Na Li

Inventor： Bin Zhao ,  Na Li

IPC: G06K9/46 ,  G06K9/34 ,  H04N9/74 ,  H04N5/225 ,  G09G5/02

CPC classification number: G06K9/46 ,  G06T7/11 ,  G06T7/194 ,  G06T7/215 ,  G06T2207/10016 ,  G06T2207/20216

Abstract: A video sequence is processed to extract one or more objects. The extracted objects are used to create a new video sequence. In particular, a user is able to select a background and/or an audio recording. Alternatively, the object extraction system automatically selects a background and/or audio recording. The extracted objects are integrated into the selected background and/or the audio recording is added to form a new video sequence.

Abstract translation: 处理视频序列以提取一个或多个对象。 提取的对象用于创建新的视频序列。 特别地，用户能够选择背景和/或音频记录。 或者，对象提取系统自动选择背景和/或音频记录。 提取的对象被集成到所选择的背景中和/或添加音频记录以形成新的视频序列。

公开(公告)号：US07173318B2

公开(公告)日：2007-02-06

申请号：US09754806

申请日：2001-01-02

Applicant: Q Z Liu ,  Bin Zhao ,  David Howard

Inventor： Q Z Liu ,  Bin Zhao ,  David Howard

IPC: H01L29/00

CPC classification number: H01L28/10 ,  H01L27/08

Abstract: Method for fabrication of on-chip inductors and related structure are disclosed. According to one embodiment, inductors are formed by patterning conductors within a certain dielectric layer in a semiconductor die. Thereafter, the entire dielectric layer in the semiconductor die is subjected to a blanket implantation or sputtering of high permeability material. According to another embodiment, a first area in a semiconductor die is covered, for example, with photoresist. A second area in the semiconductor die includes a patterned conductor which is to be used as an inductor. The patterned conductor is also covered, for example, with photoresist. The second area, excluding the covered patterned conductor, is subjected to implantation or sputtering of high permeability material. According to yet another embodiment, a first area of a semiconductor die is covered, for example, with photoresist. A second area in the semiconductor area includes a patterned conductor which is to be used as an inductor. This second area, including the patterned conductor, is subjected to implantation or sputtering of high permeability material. The implantation or sputtering of high permeability materials result in the inductors having much higher inductance values than they would otherwise have.

Abstract translation: 公开了片上电感器的制造方法和相关结构。 根据一个实施例，电感器通过在半导体管芯内的某个介电层内图案化导体而形成。 此后，对半导体管芯中的整个电介质层进行高导磁率材料的覆盖注入或溅射。 根据另一实施例，半导体管芯中的第一区域例如被光致抗蚀剂覆盖。 半导体管芯中的第二区域包括用作电感器的图案化导体。 图案化的导体也例如用光致抗蚀剂覆盖。 除了被覆盖的图案导体之外的第二区域经受高磁导率材料的注入或溅射。 根据另一个实施例，半导体管芯的第一区域例如被光致抗蚀剂覆盖。 半导体区域中的第二区域包括用作电感器的图案化导体。 包括图案化导体的该第二区域经受高磁导率材料的注入或溅射。 高磁导率材料的注入或溅射导致电感器的电感值高于原来的电感值。