公开(公告)号：US12143608B2

公开(公告)日：2024-11-12

申请号：US17874731

申请日：2022-07-27

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Virginie Drugeon ,  Kiyofumi Abe ,  Takahiro Nishi ,  Tadamasa Toma

IPC: H04N19/423 ,  H04N19/31 ,  H04N19/70

Abstract: An encoder includes circuitry and memory coupled to the circuitry. Given id indicating a lower temporal sublayer other than a highest temporal sublayer in temporal sublayers, the circuitry calculates a DPB output time [id] for a picture in the lower temporal sublayer. In doing so, the circuitry of the encoder subtracts a DPB output delta [id] provided for each of the temporal sublayers from a DPB output delay shared between the temporal sublayers, and given maxid indicating the highest temporal sublayer, calculates the DPB output delta [id] by subtracting a CPB removal delay [maxid] and an offset [id] from a CPB removal delay [id]. Next, the circuitry stores the offset [id] in a bitstream.

公开(公告)号：US12132894B2

公开(公告)日：2024-10-29

申请号：US18368140

申请日：2023-09-14

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Masato Ohkawa ,  Hideo Saitou ,  Tadamasa Toma ,  Takahiro Nishi ,  Kiyofumi Abe ,  Ryuichi Kanoh

IPC: H04N19/11 ,  H04N19/159 ,  H04N19/176 ,  H04N19/61 ,  H04N19/625

CPC classification number: H04N19/11 ,  H04N19/159 ,  H04N19/176 ,  H04N19/61 ,  H04N19/625

Abstract: An encoder that encodes a current block in a picture includes circuitry and memory. Using the memory, the circuitry: determines whether to use intra prediction for the current block; and when determining to use intra prediction, (i) performs a first transform on a residual signal of the current block using a first transform basis to generate first transform coefficients; and (ii-1) performs a second transform on the first transform coefficients using a second transform basis to generate second transform coefficients and quantizes the second transform coefficients, when an intra prediction mode of the current block is a predetermined mode or when the first transform basis is same as a predetermined transform basis; and (ii-2) quantizes the first transform coefficients without performing the second transform when the intra prediction mode is different from the predetermined mode and the first transform basis is different from the predetermined transform basis.

公开(公告)号：US20240357103A1

公开(公告)日：2024-10-24

申请号：US18763019

申请日：2024-07-03

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Chong Soon LIM ,  Hai Wei Sun ,  Han Boon Teo ,  Jing Ya Li ,  Che Wei Kuo ,  Kiyofumi Abe ,  Tadamasa Toma ,  Takahiro Nishi ,  Yusuke Kato

IPC: H04N19/117 ,  H04N19/176 ,  H04N19/51 ,  H04N19/80

CPC classification number: H04N19/117 ,  H04N19/176 ,  H04N19/51 ,  H04N19/80

Abstract: An encoder that encodes a current block to be encoded in an image is provided. The encoder includes: processor; and memory coupled to the processor, in which, in operation, the processor: generates a first prediction image based on a motion vector, the first prediction image being an image with full-pel precision; generates a second prediction image using an interpolation filter by interpolating a value at a fractional-pel position between full-pel positions included in the first prediction image; and encodes the current block based on the second prediction image, and in the using of the interpolation filter, the interpolation filter is switched between a first interpolation filter and a second interpolation filter differing in a total number of taps from the first interpolation filter.

公开(公告)号：US20240340441A1

公开(公告)日：2024-10-10

申请号：US18748771

申请日：2024-06-20

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Takashi Hashimoto ,  Kiyofumi Abe ,  Tadamasa Toma ,  Takahiro Nishi ,  Ryuichi Kanoh

IPC: H04N19/52 ,  H04N19/159 ,  H04N19/182

CPC classification number: H04N19/52 ,  H04N19/159 ,  H04N19/182

Abstract: An encoder includes: circuitry; and memory, in which using the memory, the circuitry, in affine motion compensation prediction in inter prediction for a current block, places a limit on a range within which motion estimation or motion compensation is performed, and performs the motion compensation for the current block.

公开(公告)号：US12114004B2

公开(公告)日：2024-10-08

申请号：US18065513

申请日：2022-12-13

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Kiyofumi Abe ,  Takahiro Nishi ,  Tadamasa Toma ,  Ryuichi Kanoh ,  Chong Soon Lim ,  Ru Ling Liao ,  Hai Wei Sun ,  Sughosh Pavan Shashidhar ,  Han Boon Teo ,  Jing Ya Li

IPC: H04N19/51 ,  H04N19/176 ,  H04N19/182

CPC classification number: H04N19/51 ,  H04N19/176 ,  H04N19/182

Abstract: An encoder includes circuitry and a memory coupled to the circuitry, wherein the circuitry, in operation, performs a partition process. The partition process includes calculating first values of a set of pixels between a first partition and a second partition in a current block, using a first motion vector for the first partition; calculating second values of the set of pixels, using a second motion vector for the second partition; and calculating third values of the set of pixels by weighting the first values and the second values. When a ratio of a width to a height of the current block is larger than 4 or a ratio of the height to the width of the current block is larger than 4, the circuitry disables the partition process.

公开(公告)号：US20240323444A1

公开(公告)日：2024-09-26

申请号：US18675858

申请日：2024-05-28

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Hai Wei SUN ,  Chong Soon Lim ,  Han Boon Teo ,  Jing Ya Li ,  Che Wei Kuo ,  Chu Tong Wang ,  Kiyofumi Abe ,  Takahiro Nishi ,  Tadamasa Toma

IPC: H04N19/70 ,  H04N19/124 ,  H04N19/132 ,  H04N19/186 ,  H04N19/80

CPC classification number: H04N19/70 ,  H04N19/124 ,  H04N19/132 ,  H04N19/186 ,  H04N19/80

Abstract: An encoder: includes circuitry, and memory coupled to the circuitry; stores a first parameter into a bitstream, the first parameter indicating whether a syntax element related to a chroma tool offset is present in the bitstream; when the first parameter indicates that the syntax element is present in the bitstream, (i) stores, in the bitstream, one or more second parameters that are used in deblocking filtering for a chroma sample of a current image, in addition to the syntax element, (ii) performs the deblocking filtering using the one or more second parameters, and (iii) encodes the current image; and when the first parameter indicates that the syntax element is not present in the bitstream, encodes the current image without storing the one or more second parameters into the bitstream.

公开(公告)号：US20240314296A1

公开(公告)日：2024-09-19

申请号：US18675704

申请日：2024-05-28

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Jing Ya LI ,  Chong Soon Lim ,  Han Boon Teo ,  Hai Wei Sun ,  Che Wei Kuo ,  Kiyofumi Abe ,  Takahiro Nishi ,  Tadamasa Toma ,  Yusuke Kato

IPC: H04N19/105 ,  H04N19/159 ,  H04N19/176 ,  H04N19/52

CPC classification number: H04N19/105 ,  H04N19/159 ,  H04N19/176 ,  H04N19/52

Abstract: Provided is an encoder includes: circuitry; and memory coupled to the circuitry, in which in operation, the circuitry: generates a prediction image of a current block to be processed, using a first motion vector; and updates a history based motion vector predictor (HMVP) table using a first candidate having the first motion vector, the HMVP table storing, in a first in first out (FIFO) method, a plurality of second candidates each having a second motion vector used for a processed block, and in the updating of the HMVP table, the circuitry: determines whether a size of the current block is less than or equal to a threshold size; and skips the updating of the HMVP table when the size of the current block is determined to be less than or equal to the threshold size.

公开(公告)号：US12081793B2

公开(公告)日：2024-09-03

申请号：US18226952

申请日：2023-07-27

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Kiyofumi Abe ,  Takahiro Nishi ,  Tadamasa Toma

IPC: H04N19/52 ,  H04N19/137 ,  H04N19/186 ,  H04N19/176

CPC classification number: H04N19/52 ,  H04N19/137 ,  H04N19/186 ,  H04N19/176

Abstract: An encoder includes circuitry and memory connected to the circuitry. In operation, the circuitry: derives an average value of motion vector values of two prediction candidates in a prediction candidate list for a merge mode, and registers the average value derived as new motion vector information of a new prediction candidate into the prediction candidate list; and derives new correction processing information regarding correction processing of a prediction image, and registers the new correction processing information derived into the prediction candidate list in association with the new motion vector information.

公开(公告)号：US20240291972A1

公开(公告)日：2024-08-29

申请号：US18657076

申请日：2024-05-07

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Ru Ling LIAO ,  Chong Soon Lim ,  Jing Ya Li ,  Han Boon Teo ,  Hai Wei Sun ,  Che Wei Kuo ,  Yusuke Kato ,  Tadamasa Toma ,  Kiyofumi Abe ,  Takahiro Nishi

IPC: H04N19/107 ,  H04N19/176

CPC classification number: H04N19/107 ,  H04N19/176

Abstract: An image encoder includes: circuitry; and a memory coupled to the circuitry. The circuitry, in operation: calculates first values of a current block using intra prediction, the intra prediction being limited to planar mode, the planar mode using multiple reference pixels for each pixel location of the current block; calculates second values of the current block using inter prediction; calculates third values of the current block by weighting the first values and the second values; and encodes the current block using the third values, and in the calculating of the third values, a first weight is applied to the first values and a second weight is applied to the second values, the second weight being different from the first weight.

公开(公告)号：US12075042B2

公开(公告)日：2024-08-27

申请号：US18208380

申请日：2023-06-12

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Chong Soon Lim ,  Hai Wei Sun ,  Jing Ya Li ,  Han Boon Teo ,  Che-Wei Kuo ,  Chu Tong Wang ,  Kiyofumi Abe ,  Takahiro Nishi ,  Tadamasa Toma ,  Yusuke Kato

IPC: H04N19/117 ,  H04N19/132 ,  H04N19/169 ,  H04N19/82

CPC classification number: H04N19/117 ,  H04N19/132 ,  H04N19/188 ,  H04N19/82

Abstract: An encoder includes circuitry and memory coupled to the circuitry. In operation, the circuitry: encodes information for deriving a parameter into a header of a bitstream; filters reconstructed samples in a first image using a filtering process, to generate a second image; determines whether the parameter has a predefined value; encodes a third image using the second image when the parameter has the predefined value; and encodes the third image using the first image when the parameter does not have the predefined value.