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    FINFET DEVICE WITH ISOLATED CHANNEL
    101.
    发明申请
    FINFET DEVICE WITH ISOLATED CHANNEL 有权
    具有隔离通道的FINFET器件

    公开(公告)号：US20140151746A1

    公开(公告)日：2014-06-05

    申请号：US13691070

    申请日：2012-11-30

    Applicant: STMICROELECTRONICS, INC.

    Inventor： Nicolas Loubet ,  Prasanna Khare

    IPC: H01L27/088 ,  H01L29/66

    CPC classification number: H01L27/088 ,  H01L29/66477 ,  H01L29/66795 ,  H01L29/785

    Abstract: Despite improvements in FinFETs and strained silicon devices, transistors continue to suffer performance degradation as device dimensions shrink. These include, in particular, leakage of charge between the semiconducting channel and the substrate. An isolated channel FinFET device prevents channel-to-substrate leakage by inserting an insulating layer between the channel (fin) and the substrate. The insulating layer isolates the fin from the substrate both physically and electrically. To form the isolated FinFET device, an array of bi-layer fins can be grown epitaxially from the silicon surface, between nitride columns that provide localized insulation between adjacent fins. Then, the lower fin layer can be removed, while leaving the upper fin layer, thus yielding an interdigitated array of nitride columns and semiconducting fins suspended above the silicon surface. A resulting gap underneath the upper fin layer can then be filled in with oxide to isolate the array of fin channels from the substrate.

    Abstract translation: 尽管FinFET和应变硅器件有所改进，晶体管在器件尺寸缩小的同时仍继续受到性能的降低。 这些特别包括在半导体沟道和衬底之间的电荷泄漏。 隔离沟道FinFET器件通过在沟道（鳍片）和衬底之间插入绝缘层来防止沟道对衬底的泄漏。 绝缘层物理和电气都将鳍片与衬底隔离开来。 为了形成隔离的FinFET器件，可以从硅表面，在提供相邻鳍片之间的局部绝缘的氮化物柱之间外延生长双层鳍片阵列。 然后，可以除去下部翅片层，同时留下上部翅片层，从而产生悬挂在硅表面上方的氮化物柱和半导体翅片的交错排列。 然后可以用氧化物填充在上翅片层下方的产生的间隙，以将翅片通道阵列与基底隔离。

    Semiconductor device with fin and related methods
    103.
    发明授权
    Semiconductor device with fin and related methods 有权

    公开(公告)号：US11302812B2

    公开(公告)日：2022-04-12

    申请号：US17087218

    申请日：2020-11-02

    Applicant: STMICROELECTRONICS, INC.

    Inventor： Pierre Morin ,  Nicolas Loubet

    IPC: H01L29/00 ,  H01L29/78 ,  H01L29/66 ,  H01L29/165 ,  H01L27/088

    Abstract: A semiconductor device may include a substrate, a fin above the substrate and having a channel region therein, and source and drain regions adjacent the channel region to generate shear and normal strain on the channel region. A semiconductor device may include a substrate, a fin above the substrate and having a channel region therein, source and drain regions adjacent the channel region, and a gate over the channel region. The fin may be canted with respect to the source and drain regions to generate shear and normal strain on the channel region.

    Semiconductor device with fin and related methods
    104.
    发明授权
    Semiconductor device with fin and related methods 有权

    公开(公告)号：US10854750B2

    公开(公告)日：2020-12-01

    申请号：US16680222

    申请日：2019-11-11

    Applicant: STMICROELECTRONICS, INC.

    Inventor： Pierre Morin ,  Nicolas Loubet

    IPC: H01L29/00 ,  H01L29/78 ,  H01L29/66 ,  H01L29/165 ,  H01L27/088

    Abstract: A semiconductor device may include a substrate, a fin above the substrate and having a channel region therein, and source and drain regions adjacent the channel region to generate shear and normal strain on the channel region. A semiconductor device may include a substrate, a fin above the substrate and having a channel region therein, source and drain regions adjacent the channel region, and a gate over the channel region. The fin may be canted with respect to the source and drain regions to generate shear and normal strain on the channel region.

    SEMICONDUCTOR DEVICE WITH FIN AND RELATED METHODS
    106.
    发明申请
    SEMICONDUCTOR DEVICE WITH FIN AND RELATED METHODS 审中-公开

    公开(公告)号：US20200083376A1

    公开(公告)日：2020-03-12

    申请号：US16680222

    申请日：2019-11-11

    Applicant: STMICROELECTRONICS, INC.

    Inventor： Pierre Morin ,  Nicolas Loubet

    IPC: H01L29/78 ,  H01L27/088 ,  H01L29/165 ,  H01L29/66

    Abstract: A semiconductor device may include a substrate, a fin above the substrate and having a channel region therein, and source and drain regions adjacent the channel region to generate shear and normal strain on the channel region. A semiconductor device may include a substrate, a fin above the substrate and having a channel region therein, source and drain regions adjacent the channel region, and a gate over the channel region. The fin may be canted with respect to the source and drain regions to generate shear and normal strain on the channel region.

    Facet-free strained silicon transistor
    109.
    发明授权
    Facet-free strained silicon transistor 有权

    公开(公告)号：US10134899B2

    公开(公告)日：2018-11-20

    申请号：US14983070

    申请日：2015-12-29

    Applicant: STMicroelectronics, Inc.

    Inventor： Nicolas Loubet ,  Prasanna Khare ,  Qing Liu

    IPC: H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L29/165 ,  H01L21/762 ,  H01L21/8238 ,  H01L29/16 ,  H01L29/161

    Abstract: The presence of a facet or a void in an epitaxially grown crystal indicates that crystal growth has been interrupted by defects or by certain material boundaries. Faceting can be suppressed during epitaxial growth of silicon compounds that form source and drain regions of strained silicon transistors. It has been observed that faceting can occur when epitaxial layers of certain silicon compounds are grown adjacent to an oxide boundary, but faceting does not occur when the epitaxial layer is grown adjacent to a silicon boundary or adjacent to a nitride boundary. Because epitaxial growth of silicon compounds is often necessary in the vicinity of isolation trenches that are filled with oxide, techniques for suppression of faceting in these areas are of particular interest. One such technique, presented herein, is to line the isolation trenches with SiN to provide a barrier between the oxide and the region in which epitaxial growth is intended.

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