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公开(公告)号：US09633911B2
公开(公告)日：2017-04-25
申请号：US14668482
申请日：2015-03-25
发明人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Qing Liu , Nicolas Loubet , Scott Luning
IPC分类号： H01L43/02 , H01L43/08 , H01L43/12 , H01L27/22 , H01L43/10 , H01L21/84 , H01L27/12 , H01L21/8238 , H01L27/092 , H01L29/49 , H01L29/10 , H01L29/16 , H01L29/161
CPC分类号： H01L21/845 , H01L21/823807 , H01L21/823821 , H01L21/823842 , H01L21/84 , H01L27/092 , H01L27/0922 , H01L27/0924 , H01L27/1203 , H01L27/1211 , H01L29/1054 , H01L29/16 , H01L29/161 , H01L29/4966
摘要： A method for semiconductor fabrication includes providing channel regions on a substrate including at least one Silicon Germanium (SiGe) channel region, the substrate including a plurality of regions including a first region and a second region. Gate structures are formed for a first n-type field effect transistor (NFET) and a first p-type field effect transistor (PFET) in the first region and a second NFET and a second PFET in the second region, the gate structure for the first PFET being formed on the SiGe channel region. The gate structure for the first NFET includes a gate material having a first work function and the gate structures for the first PFET, second NFET and second PFET include a gate material having a second work function such that multi-threshold voltage devices are provided.
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2.发明授权Simplified multi-threshold voltage scheme for fully depleted SOI MOSFETs 有权用于完全耗尽的SOI MOSFET的简化多阈值电压方案公开(公告)号：US09219078B2
公开(公告)日：2015-12-22
申请号：US13865795
申请日：2013-04-18
发明人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Qing Liu , Nicolas Loubet , Scott Luning
IPC分类号： H01L27/12 , H01L21/8238 , H01L27/092 , H01L29/49 , H01L21/84 , H01L29/10
CPC分类号： H01L21/845 , H01L21/823807 , H01L21/823821 , H01L21/823842 , H01L21/84 , H01L27/092 , H01L27/0922 , H01L27/0924 , H01L27/1203 , H01L27/1211 , H01L29/1054 , H01L29/16 , H01L29/161 , H01L29/4966
摘要： A method for semiconductor fabrication includes providing channel regions on a substrate including at least one Silicon Germanium (SiGe) channel region, the substrate including a plurality of regions including a first region and a second region. Gate structures are formed for a first n-type field effect transistor (NFET) and a first p-type field effect transistor (PFET) in the first region and a second NFET and a second PFET in the second region, the gate structure for the first PFET being formed on the SiGe channel region. The gate structure for the first NFET includes a gate material having a first work function and the gate structures for the first PFET, second NFET and second PFET include a gate material having a second work function such that multi-threshold voltage devices are provided.
摘要翻译： 一种用于半导体制造的方法包括在包括至少一个硅锗（SiGe）沟道区的衬底上提供沟道区，所述衬底包括包括第一区和第二区的多个区域。 对于第一区域中的第一n型场效应晶体管（NFET）和第一p型场效应晶体管（PFET）以及第二区域中的第二NFET和第二PFET形成栅极结构， 第一PFET形成在SiGe沟道区上。 用于第一NFET的栅极结构包括具有第一功函数的栅极材料，并且用于第一PFET，第二NFET和第二PFET的栅极结构包括具有第二功函数的栅极材料，使得提供多阈值电压器件。
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公开(公告)号：US10262905B2
公开(公告)日：2019-04-16
申请号：US14867797
申请日：2015-09-28
发明人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Qing Liu , Nicolas Loubet , Scott Luning
IPC分类号： H01L21/84 , H01L21/8238 , H01L27/092 , H01L29/16 , H01L29/161 , H01L27/12 , H01L29/49 , H01L29/10
摘要： A method for semiconductor fabrication includes providing channel regions on a substrate including at least one Silicon Germanium (SiGe) channel region, the substrate including a plurality of regions including a first region and a second region. Gate structures are formed for a first n-type field effect transistor (NFET) and a first p-type field effect transistor (PFET) in the first region and a second NFET and a second PFET in the second region, the gate structure for the first PFET being formed on the SiGe channel region. The gate structure for the first NFET includes a gate material having a first work function and the gate structures for the first PFET, second NFET and second PFET include a gate material having a second work function such that multi-threshold voltage devices are provided.
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公开(公告)号：US20180108571A1
公开(公告)日：2018-04-19
申请号：US15294228
申请日：2016-10-14
申请人： GLOBALFOUNDRIES INC.
IPC分类号： H01L21/8234 , H01L21/768 , H01L21/321 , H01L21/311 , H01L21/027 , H01L23/528 , H01L23/522 , H01L29/66 , H01L29/08
CPC分类号： H01L21/823475 , H01L21/0274 , H01L21/31111 , H01L21/3212 , H01L21/76802 , H01L21/76834 , H01L21/7684 , H01L21/76877 , H01L21/76895 , H01L21/823418 , H01L23/522 , H01L23/5222 , H01L23/5286 , H01L27/0207 , H01L27/14636 , H01L29/0847 , H01L29/66568
摘要： At least one method, apparatus and system disclosed involves providing an integrated circuit having metal feature flyover over an middle-of-line (MOL) feature. A first location for a non-contact intersection region between a first middle of line (MOL) interconnect feature and a metal feature in a functional cell is determined. A dielectric feature is formed over the first MOL interconnect feature at the first location. The metal feature is formed over the dielectric layer, the dielectric layer providing a predetermined amount of voltage isolation between the first MOL interconnect feature and the metal feature.
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5.发明申请公开(公告)号：US20180182674A1
公开(公告)日：2018-06-28
申请号：US15905621
申请日：2018-02-26
申请人： GLOBALFOUNDRIES INC.
IPC分类号： H01L21/8234 , H01L29/66 , H01L29/08 , H01L23/528 , H01L23/522 , H01L21/768 , H01L21/027 , H01L21/321 , H01L21/311
CPC分类号： H01L21/823475 , H01L21/0274 , H01L21/31111 , H01L21/3212 , H01L21/76802 , H01L21/76834 , H01L21/7684 , H01L21/76877 , H01L21/76895 , H01L21/823418 , H01L23/522 , H01L23/5222 , H01L23/5286 , H01L27/0207 , H01L27/14636 , H01L29/0847 , H01L29/66568
摘要： At least one method, apparatus and system disclosed involves providing an integrated circuit having metal feature flyover over an middle-of-line (MOL) feature. A first location for a non-contact intersection region between a first middle of line (MOL) interconnect feature and a metal feature in a functional cell is determined. A dielectric feature is formed over the first MOL interconnect feature at the first location. The metal feature is formed over the dielectric layer, the dielectric layer providing a predetermined amount of voltage isolation between the first MOL interconnect feature and the metal feature.
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公开(公告)号：US09947590B1
公开(公告)日：2018-04-17
申请号：US15294228
申请日：2016-10-14
申请人： GLOBALFOUNDRIES INC.
IPC分类号： H01L21/00 , H01L21/8234 , H01L21/768 , H01L21/321 , H01L21/311 , H01L21/027 , H01L23/528 , H01L23/522 , H01L29/66 , H01L29/08
CPC分类号： H01L21/823475 , H01L21/0274 , H01L21/31111 , H01L21/3212 , H01L21/76802 , H01L21/76834 , H01L21/7684 , H01L21/76877 , H01L21/76895 , H01L21/823418 , H01L23/522 , H01L23/5222 , H01L23/5286 , H01L27/0207 , H01L27/14636 , H01L29/0847 , H01L29/66568
摘要： At least one method, apparatus and system disclosed involves providing an integrated circuit having metal feature flyover over an middle-of-line (MOL) feature. A first location for a non-contact intersection region between a first middle of line (MOL) interconnect feature and a metal feature in a functional cell is determined. A dielectric feature is formed over the first MOL interconnect feature at the first location. The metal feature is formed over the dielectric layer, the dielectric layer providing a predetermined amount of voltage isolation between the first MOL interconnect feature and the metal feature.
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公开(公告)号：US10068806B2
公开(公告)日：2018-09-04
申请号：US15905621
申请日：2018-02-26
申请人： GLOBALFOUNDRIES INC.
IPC分类号： H01L21/8234 , H01L29/08 , H01L29/66 , H01L23/522 , H01L23/528 , H01L21/027 , H01L21/768 , H01L21/311 , H01L21/321 , H01L27/146
CPC分类号： H01L21/823475 , H01L21/0274 , H01L21/31111 , H01L21/3212 , H01L21/76802 , H01L21/76834 , H01L21/7684 , H01L21/76877 , H01L21/76895 , H01L21/823418 , H01L23/522 , H01L23/5221 , H01L23/5222 , H01L23/5286 , H01L27/0207 , H01L27/14636 , H01L29/0847 , H01L29/66568
摘要： At least one method, apparatus and system disclosed involves providing an integrated circuit having metal feature flyover over an middle-of-line (MOL) feature. A first location for a non-contact intersection region between a first middle of line (MOL) interconnect feature and a metal feature in a functional cell is determined. A dielectric feature is formed over the first MOL interconnect feature at the first location. The metal feature is formed over the dielectric layer, the dielectric layer providing a predetermined amount of voltage isolation between the first MOL interconnect feature and the metal feature.
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公开(公告)号：US09666488B1
公开(公告)日：2017-05-30
申请号：US15095612
申请日：2016-04-11
申请人： GLOBALFOUNDRIES Inc.
IPC分类号： H01L21/00 , H01L27/00 , H01L29/00 , H01L21/8238 , H01L21/84 , H01L21/285 , H01L27/092 , H01L27/12 , H01L29/08 , H01L29/161 , H01L29/165 , H01L29/78
CPC分类号： H01L21/823814 , H01L21/28518 , H01L21/823807 , H01L21/823864 , H01L21/823871 , H01L21/84 , H01L27/092 , H01L27/1203 , H01L29/0847 , H01L29/161 , H01L29/165 , H01L29/7838 , H01L29/7848
摘要： A method of forming a silicide layer as a pass-through contact under a gate contact between p-epilayer and n-epilayer source/drains and the resulting device are provided. Embodiments include depositing a semiconductor layer over a substrate; forming a pFET gate on a p-side of the semiconductor layer and a nFET gate on a n-side of the semiconductor layer; forming a gate contact between the pFET gate and the nFET gate; forming raised source/drains on opposite sides of each of the pFET and nFET gates; and forming a metal silicide over a first raised source/drain on the p-side and over a second raised source/drain on the n-side, wherein the metal silicide extends from the first raised source/drain to the second raised source/drain and below the gate contact between the pFET and nFET gates.
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