公开(公告)号：US5353427A

公开(公告)日：1994-10-04

申请号：US63487

申请日：1993-05-19

申请人： Kazuyasu Fujishima ,  Yoshio Matsuda ,  Mikio Asakura

发明人： Kazuyasu Fujishima ,  Yoshio Matsuda ,  Mikio Asakura

IPC分类号： G06F12/08 ,  G11C7/10

CPC分类号： G06F12/0893 ,  G11C7/1021

摘要： A semiconductor memory device comprises a DRAM memory cell array comprising a plurality of dynamic type memory cells arranged in a plurality of rows and columns, and an SRAM memory cell array comprising static type memory cells arranged in a plurality of rows and columns. The DRAM memory cell array is divided into a plurality of blocks each comprising a plurality of columns. The SRAM memory cell array is divided into a plurality of blocks each comprising a plurality of columns, corresponding to the plurality of blocks in the DRAM memory cell array. The SRAM memory cell array is used as a cache memory. At the time of cache hit, data is accessed to the SRAM memory cell array. At the time of cache miss, data is accessed to the DRAM memory cell array. On this occasion, data corresponding to one row in each of the blocks in the DRAM memory cell array is transferred to one row in the corresponding block in the SRAM memory cell array.

摘要翻译： 一种半导体存储器件包括：DRAM存储单元阵列，包括以多行和多列布置的多个动态型存储单元;以及SRAM存储单元阵列，其包括排列成多行和列的静态型存储单元。 DRAM存储单元阵列被分成多个块，每个块包括多个列。 SRAM存储单元阵列被分成多个块，每个块包括对应于DRAM存储单元阵列中的多个块的多个列。 SRAM存储单元阵列用作高速缓冲存储器。 在缓存命中时，数据被访问到SRAM存储单元阵列。 在缓存未命中时，数据被存取到DRAM存储单元阵列。 在这种情况下，对应于DRAM存储单元阵列中的每个块中的一行的数据被传送到SRAM存储单元阵列中相应块中的一行。

公开(公告)号：US5091887A

公开(公告)日：1992-02-25

申请号：US521717

申请日：1990-05-11

申请人： Mikio Asakura

发明人： Mikio Asakura

IPC分类号： G11C11/401 ,  G11C7/18 ,  G11C11/4097

CPC分类号： G11C7/18 ,  G11C11/4097

摘要： A dynamic semiconductor memory device includes a memory cell array comprising a plurality of word lines (WL.sub.0 -WL.sub.n), a plurality of bit lines (BL.sub.n -BL.sub.n+11) and a plurality of memory cells (MC) connected to intersections between the word lines and the bit lines. The plurality of bit lines include bit line pairs of two bit lines, one being a bit line for reading information of a memory cell, and the other being a bit line for providing a reference potential, and sense amplifiers (SA1-SA5) for detecting a potential difference between each bit line pair to amplify the same. The plurality of bit line pairs include bit line pairs crossing with each other such that a capacitance is balanced between adjacent bit lines, and bit line pairs having no crossing portion between which the bit line pairs crossing with each other are arranged such that a capacitance is balanced between said adjacent bit lines. Accordingly, the bit lines having the crossing portions receive the same noise from the other adjacent bit lines, and the bit lines having no crossing portion receive no noise between the paired bit lines, so that a reading potential difference can be reduced.

摘要翻译： 动态半导体存储器件包括存储单元阵列，其包括多个字线（WL0-WLn），多个位线（BLn-BLn + 11）和多个存储器单元（MC），其连接到字线 和位线。 多条位线包括两条位线的位线对，一条是用于读取存储单元的信息的位线，另一条是用于提供参考电位的位线，以及用于检测的读出放大器（SA1-SA5） 每个位线对之间的电位差放大。 多个位线对包括彼此交叉的位线对，使得相邻位线之间的电容是平衡的，并且位线对之间没有彼此交叉的位线对之间的交叉部分布置成电容为 在所述相邻位线之间平衡。 因此，具有交叉部分的位线从其他相邻位线接收相同的噪声，并且没有交叉部分的位线在成对的位线之间不接收噪声，从而可以减小读取电位差。