公开(公告)号：US06551846B1

公开(公告)日：2003-04-22

申请号：US09642751

申请日：2000-08-18

申请人： Kiyohiro Furutani ,  Mikio Asakura ,  Tetsuo Katoh

发明人： Kiyohiro Furutani ,  Mikio Asakura ,  Tetsuo Katoh

IPC分类号： G01R3126

CPC分类号： H01L22/34 ,  H01L2924/0002 ,  H01L2924/3011 ,  Y10S257/905 ,  Y10S257/906 ,  Y10S257/907 ,  Y10S257/908 ,  H01L2924/00

摘要： A test signal generating circuit generates internal test control signals from a small number of signals supplied via an address terminal in a test mode operation. According to the test control signals, the values of internal row address signal bits from an address buffer are set, while a row-related control circuit with test control function controls operations of a row selection circuit and bit line peripheral circuitry according to the test control signals. A plurality of word lines are driven simultaneously into a selected state and an acceleration test is performed according to a small number of control signals in a short period of time. Voltage stress applied between memory cell capacitors and between word lines can be accelerated with a small number of control signals.

摘要翻译： 测试信号发生电路在测试模式操作中从经由地址终端提供的少量信号产生内部测试控制信号。 根据测试控制信号，设置来自地址缓冲器的内部行地址信号位的值，而具有测试控制功能的行相关控制电路根据测试控制来控制行选择电路和位线外围电路的操作 信号。 多个字线被同时驱动到选择状态，并且在短时间段内根据少量的控制信号执行加速度测试。 存储单元电容器和字线之间施加的电压应力可以用少量的控制信号加速。

公开(公告)号：US06377512B1

公开(公告)日：2002-04-23

申请号：US09666133

申请日：2000-09-20

申请人： Takeshi Hamamoto ,  Takuya Ariki ,  Mikio Asakura ,  Takayuki Nishiyama

发明人： Takeshi Hamamoto ,  Takuya Ariki ,  Mikio Asakura ,  Takayuki Nishiyama

IPC分类号： G11C818

CPC分类号： G11C8/12 ,  G11C7/1006 ,  G11C7/1051 ,  G11C7/1072

摘要： Data buses are arranged in a one-to-one correspondence to pads. These data buses are arranged in common to a plurality of memory arrays. A read data driver is rendered active selectively according to a word configuration to switch equivalently the connection between a memory array and a data bus.

摘要翻译： 数据总线与焊盘一一对应地布置。 这些数据总线被共同布置成多个存储器阵列。 读数据驱动器根据字配置选择性地被有效地切换以切换存储器阵列和数据总线之间的连接。

公开(公告)号：US06269038B1

公开(公告)日：2001-07-31

申请号：US09556290

申请日：2000-04-24

申请人： Takashi Itou ,  Yasuhiko Tsukikawa ,  Kengo Aritomi ,  Mikio Asakura

发明人： Takashi Itou ,  Yasuhiko Tsukikawa ,  Kengo Aritomi ,  Mikio Asakura

IPC分类号： G11C700

CPC分类号： G11C29/46

摘要： There is provided a test mode decision circuit which in the first WCBR cycle responds to an address key by activating a test mode entry signal and with the test mode entry signal activated in the second WCBR cycle responds to an address key by selectively activating test mode signals. In addition to a test mode signal having been activated, the test mode decision circuit further activates another test mode signal. Thus the DRAM hardly enter a test mode erroneously and is also capable of entering more than one test mode simultaneously.

摘要翻译： 提供了测试模式判定电路，其在第一WCBR周期中通过激活测试模式输入信号来响应地址键，并且在第二WCBR周期中激活的测试模式输入信号通过选择性地激活测试模式信号来响应地址键 。 测试模式判定电路除了测试模式信号被激活之外，还激活另一个测试模式信号。 因此，DRAM几乎不会错误地进入测试模式，并且还能够同时进入多个测试模式。

公开(公告)号：US6157588A

公开(公告)日：2000-12-05

申请号：US229343

申请日：1999-01-13

申请人： Yasuhiro Matsumoto ,  Mikio Asakura ,  Takeshi Hamamoto ,  Kei Hamade

发明人： Yasuhiro Matsumoto ,  Mikio Asakura ,  Takeshi Hamamoto ,  Kei Hamade

IPC分类号： G11C11/407 ,  G11C7/18 ,  G11C11/401 ,  G11C11/409 ,  G11C11/4097 ,  H01L21/8242 ,  H01L27/108 ,  G11C7/02

CPC分类号： G11C7/18 ,  G11C11/4097

摘要： First and second global input/output lines are twisted between first and second main blocks. First and second SD signal lines in the first main block are respectively arranged adjacent to first and second global input/output lines. First and second SD signal lines in the second main block are respectively arranged adjacent to the second and first global input/output lines. An SD signal supplied for the first or second SD signal line makes noises applied to the first and second global input/output lines identical, so that an influence by the noises is substantially eliminated between the first and second global input/output lines. As a result, the global input/output line is provided with higher resistance to noise without any increase in a layout area.

摘要翻译： 第一和第二全局输入/输出线在第一和第二主块之间扭转。 第一主块中的第一和第二SD信号线分别布置成与第一和第二全局输入/输出线相邻。 第二主块中的第一和第二SD信号线分别布置成与第二和第一全局输入/输出线相邻。 为第一或第二SD信号线提供的SD信号对第一和第二全局输入/输出线施加相同的噪声，使得在第一和第二全局输入/输出线之间基本上消除了噪声的影响。 因此，全球输入/输出线路具有更高的抗噪声能力，而不会增加布局面积。

公开(公告)号：US5999464A

公开(公告)日：1999-12-07

申请号：US58885

申请日：1998-04-13

申请人： Hideto Hidaka ,  Mikio Asakura ,  Kiyohiro Furutani ,  Tetsuo Kato

发明人： Hideto Hidaka ,  Mikio Asakura ,  Kiyohiro Furutani ,  Tetsuo Kato

IPC分类号： G11C11/413 ,  G11C11/401 ,  G11C29/00 ,  G11C29/04 ,  G11C29/14 ,  G11C29/24

CPC分类号： G11C29/24

摘要： A semiconductor memory device includes a first test row decoder (9a) for selecting memory cells in normal rows in a test mode, a second test row decoder (9b) for selecting spare memory cell rows, a first test column decoder (10a) for selecting memory cells in normal columns, and a second test column decoder (10b) for selecting spare memory cell columns. A control circuit (11) may perform switching between four combinations of the row and column decoders by using a control signal (SRT) and a control signal (SCT). All spare memory cells are tested prior to reparation of a defective memory cell for yield enhancement.

公开(公告)号：US5978299A

公开(公告)日：1999-11-02

申请号：US222793

申请日：1998-12-30

申请人： Kyoji Yamasaki ,  Tadaaki Yamauchi ,  Mikio Asakura

发明人： Kyoji Yamasaki ,  Tadaaki Yamauchi ,  Mikio Asakura

IPC分类号： G11C11/413 ,  G11C5/14 ,  G11C11/401 ,  G11C11/407 ,  G11C11/409 ,  G11C11/34

CPC分类号： G11C5/147

摘要： A semiconductor memory device includes a memory cell array, peripheral circuits including a column decoder for connecting a word line, and a VDC circuit for peripherals, for generating an internal power supply voltage based on an external power supply voltage. VDC circuit for peripherals supplies the internal power supply voltage to peripheral circuits including the column decoder, other than the sense amplifier, output buffer and internal initial stage. The supplying capability of the VDC circuit for peripherals is increased in response to a VDCE signal which is output from a clock generation circuit when column decoder is activated. Therefore, even when power consumption in the peripheral circuit is increased as the column decoder is activated, sufficient power can be supplied to the peripheral circuit.

公开(公告)号：US5970507A

公开(公告)日：1999-10-19

申请号：US676963

申请日：1996-07-08

申请人： Tetsuo Kato ,  Kiyohiro Furutani ,  Hideto Hidaka ,  Mikio Asakura

发明人： Tetsuo Kato ,  Kiyohiro Furutani ,  Hideto Hidaka ,  Mikio Asakura

IPC分类号： G11C11/403 ,  G11C11/406 ,  G11C11/409 ,  G06F12/00

CPC分类号： G11C11/406

摘要： In a semiconductor memory device, a self refresh cycle program circuit is provided and a refresh operation is conducted in accordance with one of the refresh cycles programmed in the refresh-cycle program circuit. The refresh cycle of the self-refresh mode is selected from a plurality of refresh-cycle types. A plurality of refresh modes allows a refresh cycle to be selected from a plurality of refresh-cycle types in accordance with a selected refresh mode.

摘要翻译： 在半导体存储器件中，提供自刷新周期程序电路，并且根据在刷新周期程序电路中编程的刷新周期之一进行刷新操作。 从多个刷新周期类型中选择自刷新模式的刷新周期。 多个刷新模式允许根据所选择的刷新模式从多个刷新周期类型中选择刷新周期。

公开(公告)号：US5969984A

公开(公告)日：1999-10-19

申请号：US124508

申请日：1998-07-29

申请人： Yuichiro Komiya ,  Tsukasa Ooishi ,  Hideto Hidaka ,  Mikio Asakura

发明人： Yuichiro Komiya ,  Tsukasa Ooishi ,  Hideto Hidaka ,  Mikio Asakura

IPC分类号： H01L29/40 ,  G11C5/14 ,  G11C7/10 ,  G11C11/407 ,  G11C11/408 ,  H01L21/822 ,  H01L21/8238 ,  H01L27/04 ,  H01L27/092 ,  H03K19/003 ,  H03K19/0175 ,  H03K19/0944 ,  G11C13/00

CPC分类号： G11C7/1078 ,  G11C5/145 ,  G11C5/146 ,  G11C5/147

摘要： The level converting circuit includes a first current cutting circuit, a second current cutting circuit, a level shift circuit and an inverter. The first current cutting circuit includes two PMOS transistors connected to a node having a boosted potential Vpp. The second current cutting circuit includes two NMOS transistor connected to a ground node. The level shift circuits include two PMOS transistors and two NMOS transistors. Before a through current flows between the node having the boosted potential Vpp and the ground node, any of the transistor included in the first current cutting circuit and any of the transistors included in the second current cutting circuits are turned off. Therefore, through current between the node having the boosted potential Vbb and the ground node can be prevented.

摘要翻译： 电平转换电路包括第一电流切断电路，第二电流切断电路，电平移位电路和反相器。 第一电流切割电路包括连接到具有升压电位Vpp的节点的两个PMOS晶体管。 第二电流切断电路包括连接到接地节点的两个NMOS晶体管。 电平移位电路包括两个PMOS晶体管和两个NMOS晶体管。 在直流电流在具有升压电位Vpp的节点和接地节点之间流动之前，包括在第一电流切割电路中的任何晶体管和包括在第二电流切割电路中的任何晶体管都被截止。 因此，可以防止具有升压电位Vbb的节点与接地节点之间的电流。

公开(公告)号：US5966045A

公开(公告)日：1999-10-12

申请号：US624828

申请日：1996-03-27

申请人： Mikio Asakura

发明人： Mikio Asakura

IPC分类号： G11C11/407 ,  G11C7/10 ,  G11C11/409 ,  G11C11/417 ,  G05F1/10

CPC分类号： G11C7/1078

摘要： A power supply for supplying a power supply potential to a first stage input buffer circuit of a semiconductor device is changed according to the types of first stage input circuits. For example, an external power supply potential is supplied without change in a value from an external power supply to a first stage input buffer circuit to which a signal which activates a circuit provided in the subsequent stage only by transition from an "H" level to an "L" level such as an RAS signal. Thus, reduction in power consumption can be achieved. A stable internal power supply potential obtained by down-converting an external power supply potential is supplied from an internal power supply to a first stage input circuit to which a signal which activates a circuit provided in the subsequent stage by any one of transitions from an "L" level to an "H" level and from an "H" level to an "L" level. Thus, output information can be stabilized.

摘要翻译： 根据第一级输入电路的类型，改变向半导体器件的第一级输入缓冲电路提供电源电位的电源。 例如，外部电源电位从外部电源到第一级输入缓冲电路的值不被改变，在第一级输入缓冲电路中仅通过从“H”电平转换到后级中提供的电路的信号 一个“L”电平，如+ E，ovs RAS + EE信号。 因此，可以实现功耗的降低。 通过对外部电源电位进行下变频而获得的稳定的内部电源电位从内部电源提供给第一级输入电路，在第一级输入电路中，通过任何一种从“ L“电平变为”H“电平，从”H“电平变为”L“电平。 因此，可以稳定输出信息。

公开(公告)号：US5917766A

公开(公告)日：1999-06-29

申请号：US978594

申请日：1997-11-26

申请人： Takaharu Tsuji ,  Mikio Asakura ,  Tadaaki Yamauchi ,  Koji Tanaka

发明人： Takaharu Tsuji ,  Mikio Asakura ,  Tadaaki Yamauchi ,  Koji Tanaka

IPC分类号： G11C29/34 ,  G11C29/50 ,  G11C7/00

CPC分类号： G11C29/34 ,  G11C29/50 ,  G11C11/401

摘要： A semiconductor memory device that operates in various modes such as in a normal operation mode and a disturb accelerated test mode in which two word lines are activated simultaneously, includes a boosting power supply circuit, a boosted voltage supply line, and an input terminal connected to the boosted voltage supply line. In a disturb accelerated test mode or in a burn-in test mode, an external voltage is supplied from an external power supply to the input terminal. A word line is reliably boosted in voltage in a disturb accelerated test mode.

摘要翻译： 一种半导体存储器件，其工作在诸如正常操作模式和同时激活两个字线的干扰加速测试模式的各种模式中，包括升压电源电路，升压电源线​​和连接到 升压电源线​​。 在干扰加速测试模式或老化测试模式下，外部电源从外部电源提供给输入端。 在干扰加速测试模式下，字线可靠地升高电压。