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公开(公告)号：US5588130A
公开(公告)日：1996-12-24
申请号：US283367
申请日：1994-08-01
CPC分类号： G06F12/0893 , G11C7/1021
摘要： A semiconductor memory device comprises a DRAM memory cell array comprising a plurality of dynamic type memory cells arranged in a plurality of rows and columns, and an SRAM memory cell array comprising static type memory cells arranged in a plurality of rows and columns. The DRAM memory cell array is divided into a plurality of blocks each comprising a plurality of columns. The SRAM memory cell array is divided into a plurality of blocks each comprising a plurality of columns, corresponding to the plurality of blocks in the DRAM memory cell array. The SRAM memory cell array is used as a cache memory. At the time of cache hit, data is accessed to the SRAM memory cell array. At the time of cache miss, data is accessed to the DRAM memory cell array. On this occasion, data corresponding to one row in each of the blocks in the DRAM memory cell array is transferred to one row in the corresponding block in the SRAM memory cell array.
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公开(公告)号：US5014241A
公开(公告)日：1991-05-07
申请号：US337219
申请日：1989-04-12
IPC分类号： G11C11/401 , G11C5/02 , G11C5/06 , G11C7/14 , G11C7/18 , G11C11/4096 , G11C11/4097 , G11C11/4099 , H01L21/8242 , H01L27/108
CPC分类号： G11C5/025 , G11C11/4096 , G11C11/4097 , G11C11/4099 , G11C5/063 , G11C7/14 , G11C7/18
摘要： Each of sense amplifiers is coupled to two bit lines with another bit line being interposed therebetween. Information stored in a memory cell is read out onto one of the two bit lines coupled to each of the sense ampliers, while a reference potential is read out onto the other bit line. Outside of the two bit lines, a reference potential is respectively read out onto other bit lines adjacent to the two bit lines. The information stored in the memory cell is read out onto the other bit line between the two bit lines.
摘要翻译： 读出放大器中的每一个耦合到两个位线，另一个位线插在它们之间。 存储在存储器单元中的信息被读出到耦合到每个读出放大器的两个位线中的一个，同时将参考电位读出到另一个位线上。 在两个位线之外，将参考电位分别读出到与两个位线相邻的其它位线上。 存储在存储单元中的信息被读出到两个位线之间的另一位线上。
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公开(公告)号：US06404691B1
公开(公告)日：2002-06-11
申请号：US08472770
申请日：1995-06-07
IPC分类号： G11C700
CPC分类号： G06F12/0893 , G11C7/1021
摘要： A semiconductor memory device comprises a DRAM memory cell array comprising a plurality of dynamic type memory cells arranged in a plurality of rows and columns, and an SRAM memory cell array comprising static type memory cells arranged in a plurality of rows and columns. The DRAM memory cell array is divided into a plurality of blocks each comprising a plurality of columns. The SRAM memory cell array is divided into a plurality of blocks each comprising a plurality of columns, corresponding to the plurality of blocks in the DRAM memory cell array. The SRAM memory cell array is used as a cache memory. At the time of cache hit, data is accessed to the SRAM memory cell array. At the time of cache miss, data is accessed to the DRAM memory cell array. On this occasion, data corresponding to one row in each of the blocks in the DRAM memory cell array is transferred to one row in the corresponding block in the SRAM memory cell array.
摘要翻译： 一种半导体存储器件包括：DRAM存储单元阵列，包括以多行和多列布置的多个动态型存储单元;以及SRAM存储单元阵列，其包括排列成多行和列的静态型存储单元。 DRAM存储单元阵列被分成多个块，每个块包括多个列。 SRAM存储单元阵列被分成多个块，每个块包括对应于DRAM存储单元阵列中的多个块的多个列。 SRAM存储单元阵列用作高速缓冲存储器。 在缓存命中时，数据被访问到SRAM存储单元阵列。 在缓存未命中时，数据被存取到DRAM存储单元阵列。 在这种情况下，对应于DRAM存储单元阵列中的每个块中的一行的数据被传送到SRAM存储单元阵列中相应块中的一行。
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公开(公告)号：US5226147A
公开(公告)日：1993-07-06
申请号：US564657
申请日：1990-08-09
CPC分类号： G06F12/0893 , G11C7/1021
摘要： A semiconductor memory device comprises a DRAM memory cell array comprising a plurality of dynamic type memory cells arranged in a plurality of rows and columns, and an SRAM memory cell array comprising static type memory cells arranged in a plurality of rows and columns. The DRAM memory cell array is divided into a plurality of blocks each comprising a plurality of columns. The SRAM memory cell array is divided into a plurality of blocks each comprising a plurality of columns, corresponding to the plurality of blocks in the DRAM memory cell array. The SRAM memory cell array is used as a cache memory. At the time of cache hit, data is accessed to the SRAM memory cell array. At the time of cache miss, data is accessed to the DRAM memory cell array. On this occasion, data corresponding to one row in each of the blocks in the DRAM memory cell array is transferred to one row in the corresponding block in the SRAM memory cell array.
摘要翻译： 一种半导体存储器件包括：DRAM存储单元阵列，包括以多行和多列布置的多个动态型存储单元;以及SRAM存储单元阵列，其包括排列成多行和列的静态型存储单元。 DRAM存储单元阵列被分成多个块，每个块包括多个列。 SRAM存储单元阵列被分成多个块，每个块包括对应于DRAM存储单元阵列中的多个块的多个列。 SRAM存储单元阵列用作高速缓冲存储器。 在缓存命中时，数据被访问到SRAM存储单元阵列。 在缓存未命中时，数据被存取到DRAM存储单元阵列。 在这种情况下，对应于DRAM存储单元阵列中的每个块中的一行的数据被传送到SRAM存储单元阵列中相应块中的一行。
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5.发明授权Semiconductor memory device with cache memory addressable by block within each column 失效具有高速缓存存储器的半导体存储器件可在每列内通过块寻址
公开(公告)号：US4926385A
公开(公告)日：1990-05-15
申请号：US228589
申请日：1988-08-05
IPC分类号： G11C11/401 , G06F12/08 , G11C7/10 , G11C8/12 , G11C11/41
CPC分类号： G11C7/103 , G06F12/0893 , G11C8/12
摘要： A semiconductor memory includes a memory cell array having a plurality of bit lines and a plurality of word lines arranged intersecting with the bit lines. A plurality of memory cells are arranged at intersections of the bit lines and the word lines, respectively. Word line selecting circuitry selects one of the word lines responsive to a row address and reads out to each of the bit lines information stored in the memory cell associated with the selected word line. A plurality of sense amplifiers are associated with corresponding rows of the memory for detecting and amplifying the information stored in respective memory cells. A first column selector circuit selects the sense amplifiers corresponding to a column address when the column address is applied and reads information held in the sense amplifier. Blocks are formed by dividing the memory cell array into groups of bit lines, each of the groups comprising a predetermined number of bit lines with block information transferred simultaneously from corresponding ones of the groups of bit lines of a selected block when the column address corresponding to the selected block is applied. Data registers hold information of an associated block. A second column selector reads data corresponding to the column address from the data register when the column address is applied.
摘要翻译： 半导体存储器包括具有多个位线的存储单元阵列和与位线相交的多个字线。 多个存储单元分别布置在位线和字线的交点处。 字线选择电路响应于行地址选择一个字线，并读出存储在与所选字线相关联的存储单元中的每一个位线信息。 多个读出放大器与存储器的相应行相关联，用于检测和放大存储在相应存储单元中的信息。 当应用列地址时，第一列选择器电路选择对应于列地址的读出放大器，并读取保持在读出放大器中的信息。 通过将存储单元阵列划分成位线组来形成块，每个组包括预定数量的位线，其中块信息同时从对应于所选块的位线的位线的相应位组传送 应用所选的块。 数据寄存器保存相关块的信息。 当应用列地址时，第二列选择器从数据寄存器读取与列地址对应的数据。
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6.发明授权Semiconductor memory device for simple cache system with selective coupling of bit line pairs 失效半导体存储器件，用于具有位线对选择性耦合的简单缓存系统
公开(公告)号：US5353427A
公开(公告)日：1994-10-04
申请号：US63487
申请日：1993-05-19
CPC分类号： G06F12/0893 , G11C7/1021
摘要： A semiconductor memory device comprises a DRAM memory cell array comprising a plurality of dynamic type memory cells arranged in a plurality of rows and columns, and an SRAM memory cell array comprising static type memory cells arranged in a plurality of rows and columns. The DRAM memory cell array is divided into a plurality of blocks each comprising a plurality of columns. The SRAM memory cell array is divided into a plurality of blocks each comprising a plurality of columns, corresponding to the plurality of blocks in the DRAM memory cell array. The SRAM memory cell array is used as a cache memory. At the time of cache hit, data is accessed to the SRAM memory cell array. At the time of cache miss, data is accessed to the DRAM memory cell array. On this occasion, data corresponding to one row in each of the blocks in the DRAM memory cell array is transferred to one row in the corresponding block in the SRAM memory cell array.
摘要翻译： 一种半导体存储器件包括：DRAM存储单元阵列，包括以多行和多列布置的多个动态型存储单元;以及SRAM存储单元阵列，其包括排列成多行和列的静态型存储单元。 DRAM存储单元阵列被分成多个块，每个块包括多个列。 SRAM存储单元阵列被分成多个块，每个块包括对应于DRAM存储单元阵列中的多个块的多个列。 SRAM存储单元阵列用作高速缓冲存储器。 在缓存命中时，数据被访问到SRAM存储单元阵列。 在缓存未命中时，数据被存取到DRAM存储单元阵列。 在这种情况下，对应于DRAM存储单元阵列中的每个块中的一行的数据被传送到SRAM存储单元阵列中相应块中的一行。
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7.发明授权Semiconductor memory device having an SRAM as a cache memory integrated on the same chip and operating method thereof 失效具有集成在同一芯片上的作为高速缓存存储器的SRAM的半导体存储器件及其操作方法
公开(公告)号：US5509132A
公开(公告)日：1996-04-16
申请号：US283487
申请日：1994-08-01
IPC分类号： G06F12/08 , G11C7/10 , G11C8/00 , G11C11/401 , G11C11/41
CPC分类号： G06F12/0893 , G11C7/1051
摘要： A cache DRAM (100) includes a DRAM memory array (11) accessed by a row address signal and a column address signal, an SRAM memory array (21) accessed by the column address signal, and an ECC circuit (30). The DRAM memory array (11) is divided into a plurality of blocks (B1 to B64), each including a plurality of columns. The SRAM memory array (21) includes 4 ways (W1 to W4). In determining a cache hit/cache miss, a column address signal is inputted. Consequently, the SRAM memory array (21) is accessed and data are read from each of the ways. When a cache hit occurs, one way is selected in response to an externally applied way address signal, and data from that way are outputted. When a cache miss occurs, the column address signal is latched and the row address signal is applied. The DRAM array (11) is accessed in accordance with the row address signal and the latched column address signal.
摘要翻译： 缓存DRAM（100）包括通过行地址信号和列地址信号访问的DRAM存储器阵列（11），由列地址信号访问的SRAM存储器阵列（21）和ECC电路（30）。 DRAM存储器阵列（11）被分成多个块（B1至B64），每个块包括多个列。 SRAM存储器阵列（21）包括4路（W1至W4）。 在确定高速缓存命中/高速缓存未命中时，输入列地址信号。 因此，访问SRAM存储器阵列（21）并且从每种方式读取数据。 当发生高速缓存命中时，响应于外部施加的方式地址信号选择一种方式，并且从该方式输出数据。 当发生高速缓存未命中时，锁存列地址信号并应用行地址信号。 根据行地址信号和锁存列地址信号来访问DRAM阵列（11）。
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8.发明授权Semiconductor memory device with a built-in cache memory and operating method thereof 失效具有内置缓存存储器的半导体存储器件及其操作方法
公开(公告)号：US5226139A
公开(公告)日：1993-07-06
申请号：US637872
申请日：1991-01-08
IPC分类号： G06F9/38 , G06F12/08 , G11C11/401 , G11C11/408 , G11C11/4096 , G11C11/41
CPC分类号： G06F9/3824 , G06F12/0893 , G11C11/408 , G11C11/4096
摘要： A semiconductor memory device with a built-in cache memory comprises a memory cell array (1). The memory cell array (1) is divided into a plurality of blocks (B1 to B16). Each block is divided into a plurality of sub blocks each having a plurality of columns. At the time of a cache hit, block address signals (B0, B1) and a column address signal (CA) are simultaneously applied. Any of the plurality of blocks (B1 to B16) is selected in response to the block address signals (B0, B1). At the same time, any of the plurality of registers (16a) corresponding to the selected block is selected in response to the column address signal (CA). The data stored in the register (16a) is thereby read out at a high speed
摘要翻译： 具有内置高速缓冲存储器的半导体存储器件包括存储单元阵列（1）。 存储单元阵列（1）被分成多个块（B1〜B16）。 每个块被分成多个子块，每个子块具有多个列。 在缓存命中时，同时施加块地址信号（B0，B1）和列地址信号（CA）。 响应于块地址信号（B0，B1）选择多个块（B1至B16）中的任一个。 同时，响应于列地址信号（CA）选择对应于所选块的多个寄存器（16a）中的任何一个。 因此，存储在寄存器（16a）中的数据被高速读出
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9.发明授权Semiconductor memory device containing a cache and an operation method thereof 失效包含高速缓存的半导体存储器件及其操作方法
公开(公告)号：US5179687A
公开(公告)日：1993-01-12
申请号：US542682
申请日：1990-06-25
IPC分类号： G06F12/08 , G11C11/4096
CPC分类号： G06F12/0893 , G11C11/4096
摘要： A DRAM for use in a simple cache memory system comprises a memory cell array divided into a plurality of blocks, a plurality of data registers provided corresponding to the respective blocks of the array for latching memory cell data of the corresponding blocks, and a selector responsive to a row address strobe signal for selecting access to either the data registers or the memory cell array. Upon cache hit, the row address strobe signal is inactivated to cause the selector to select the access to the data registers. Upon cache miss, the row address strobe signal is activated to cause the selector to select the access to the memory cell array.
摘要翻译： 用于简单高速缓冲存储器系统的DRAM包括被划分成多个块的存储单元阵列，与阵列的各个块对应地提供的多个数据寄存器，用于锁存相应块的存储单元数据，以及响应于选择器 用于选择对数据寄存器或存储单元阵列的访问的行地址选通信号。 缓存命中后，行地址选通信号被取消激活，使选择器选择对数据寄存器的访问。 在缓存未命中时，行地址选通信号被激活以使选择器选择对存储单元阵列的访问。
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公开(公告)号：US4953164A
公开(公告)日：1990-08-28
申请号：US254233
申请日：1988-10-06
IPC分类号： G11C11/413 , G06F11/10 , G06F12/08 , G11C11/401 , G11C29/00 , G11C29/42
CPC分类号： G06F11/1064 , G06F12/0802
摘要： There are provided a first memory cell array and a second memory cell array. The first memory cell array comprises a dynamic RAM and the second memory cell array comprises a static RAM. In addition, the second memory cell array has smaller capacity than that of the first memory cell array. An error correcting circuit, a check bit generating circuit and a register are connected between the first memory cell array and the second memory cell array. Data which is frequently accessed is transferred from the first memory cell array to the second memory cell array and stored therein. Access is made to the second memory cell array. When data which is required is not in the second memory cell array, access is made to the first memory cell array. At the time of transferring data from the first memory cell array to the second memory cell array, errors are corrected by the error correcting circuit. The check bit generating circuit is responsive to data whose error is corrected by the error correcting circuit for generating new check bits.
摘要翻译： 提供了第一存储单元阵列和第二存储单元阵列。 第一存储单元阵列包括动态RAM，第二存储单元阵列包括静态RAM。 此外，第二存储单元阵列具有比第一存储单元阵列小的容量。 纠错电路，校验位产生电路和寄存器连接在第一存储单元阵列和第二存储单元阵列之间。 频繁访问的数据从第一存储单元阵列传送到第二存储单元阵列并存储在其中。 访问第二个存储单元阵列。 当所需的数据不在第二存储单元阵列中时，对第一存储单元阵列进行访问。 在将数据从第一存储单元阵列传送到第二存储单元阵列时，错误校正电路校正错误。 校验位产生电路响应于错误被纠错电路校正的数据，用于产生新的校验位。
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