Apparatus for convolutional self-doubly orthogonal encoding and decoding
    101.
    发明授权
    Apparatus for convolutional self-doubly orthogonal encoding and decoding 失效
    用于卷积自双向正交编码和解码的装置

    公开(公告)号:US6167552A

    公开(公告)日:2000-12-26

    申请号:US942787

    申请日:1997-10-02

    IPC分类号: H03M13/23 H03M13/43 H03M13/03

    CPC分类号: H03M13/43 H03M13/23

    摘要: An encoder and decoder for generating and decoding convolutional codes of improved orthogonality. In an exemplary embodiment the encoder includes a K-bit length shift register for receiving an input serial stream of information bits and providing for each input bit a K-bit parallel output to a self-doubly orthogonal code sequence generator. The encoded symbol stream is threshold decoded iteratively using the inversion of the convolutional self-doubly orthogonal parity code generators.

    摘要翻译: 一种用于产生和解码具有改进的正交性的卷积码的编码器和解码器。 在示例性实施例中,编码器包括用于接收输入串行信息比特的K比特长度移位寄存器,并向每个输入比特提供一个K比特并行输出到一个双重正交码序列发生器。 使用卷积自双向正交奇偶校验码生成器的反转迭代地编码符号流进行阈值解码。

    Data-reproducing device
    102.
    发明授权
    Data-reproducing device 失效
    数据再生装置

    公开(公告)号:US6154867A

    公开(公告)日:2000-11-28

    申请号:US34330

    申请日:1998-03-04

    申请人: Satoshi Itoi

    发明人: Satoshi Itoi

    摘要: A data-reproducing device includes: a subtraction absolute value circuit for calculating a substraction absolute value from pre-equalized reproduce data and estimate data output from RAM, outputting the subtraction absolute value as branchmetrics; a comparison and selection circuit for comparing addition values of the branchmetrics and previously calculated pathmetrics are added, selecting a smaller one of the values as the result of comparison, outputting the smaller one of the values as new pathmetric as well as a selection signal as to which of the values is selected; a path memory circuit for storing the selection signal, obtaining the most probable path by unifying paths, outputting the most probable data according to the most probable path; a RAM circuit for outputting estimate data judged to be closest to the pre-equalized reproduce data by using a present output of the path memory circuit as an address; and a data correction circuit for renewing an internal data of the RAM circuit based upon a data obtained by using, as an address, the pre-equalized reproduce data delayed by a predetermined value and continuous data output from the path memory circuit.

    摘要翻译: 数据再现装置包括:减法绝对值电路,用于从预均衡再现数据计算减法绝对值和从RAM输出的估计数据,输出减法绝对值作为分支测量; 添加用于比较分支测量的加法值和先前计算的路径测量值的比较和选择电路,作为比较结果选择较小的一个值,将较小的一个值作为新的测量路径输出,以及选择信号 选择哪个值? 用于存储选择信号的路径存储电路,通过统一路径获得最可能的路径,根据最可能的路径输出最可能的数据; RAM电路,用于通过使用路径存储器电路的当前输出作为地址来输出被判断为最接近预均衡再现数据的估计数据; 以及数据校正电路,用于基于通过使用延迟了预定值的预均衡再现数据和从路径存储电路输出的连续数据作为地址而获得的数据来更新RAM电路的内部数据。

    Rate 24/25 (0,9) code method and system for PRML recording channels
    103.
    发明授权
    Rate 24/25 (0,9) code method and system for PRML recording channels 有权
    为PRML录制通道的速率24/25(0,9)码方法和系统

    公开(公告)号:US6130629A

    公开(公告)日:2000-10-10

    申请号:US205319

    申请日:1998-12-04

    摘要: A system and method employing a rate 24/25 (0,9) code constructed in accordance with a data byte interleaved with a rate 16/17 (0,5) codeword formed from two data bytes limits the number of consecutive zeros seen by a channel to nine. The 16/17 (0,5) codeword is formed from the two data bytes in accordance with a set of pivot bits and a set of corrections for predefined code violations. The additional data byte is interleaved into the 16/17 (0,5) codeword by splitting the byte into a pair of portions and inserting the portions into the 16/17 (0,5) codeword at locations adjacent to predefined ones of the pivot bits. The rate 24/25 (0,9) code is suitable for magnetic or similar recording media and may be employed in partial response maximum likelihood read channels. A feature of the constructed code is a high transition density which allows for more frequent timing and gain control updates, which results in lower required channel input signal to noise ratio for a given channel performance.

    摘要翻译: 使用根据与由两个数据字节形成的速率16/17(0.5)码字交织的数据字节构成的速率24/25(0,9)码的系统和方法限制了由 渠道九。 16/17(0,5)码字是根据一组枢轴比特和一组用于预定义代码违例的校正从两个数据字节形成的。 通过将该字节分割成一对部分并将这些部分插入邻近预定义枢纽的位置的16/17(0,5)码字中,附加数据字节被交织到16/17(0,5)码字中 位。 速率24/25(0,9)代码适用于磁性或类似的记录介质,并可用于部分响应最大似然读取通道。 构造的代码的特征是高转换密度,其允许更频繁的定时和增益控制更新,这导致给定信道性能所需的信道输入信噪比更低。

    Soft decision method and receiver
    104.
    发明授权
    Soft decision method and receiver 失效
    软判决方法和接收方

    公开(公告)号:US6115435A

    公开(公告)日:2000-09-05

    申请号:US960669

    申请日:1997-10-30

    摘要: When the received symbol is located (FIG. 4) within one of regions G, H, I, L, M, N, Q, R, and S, 2 bits are decided to be most reliable to obtain their soft decision values=0 or 7. As for the remaining 2 bits, a soft decision value=0 to 7 is decided by soft decision in the I- or Q-axis direction. When the received symbol is located within one of regions A, E, U, and Y, all the 4 bits are decided to obtain their soft decision values=0 or 7. When the received symbol is located with one of regions B, C, D, F, J, K, 0, P, T, V, W, and X, 3 bits are decided to be most reliable to obtain their soft decision values=0 or 7. As for the remaining 1 bit, a soft decision value=0 to 7 is obtained by soft decision in the I- or Q-axis direction. A soft decision method that can implement soft decision in multilevel (amplitude and/or phase) modulation and can fully exhibit the correction performance of maximum likelihood coding can be provided.

    摘要翻译: 当区域G,H,I,L,M,N,Q,R和S中的一个接收到的符号位于(图4)时,确定2位最可靠以获得它们的软判决值= 0 对于剩余的2位,通过在I或Q轴方向上的软判决来决定软判定值= 0至7。 当接收到的符号位于区域A,E,U和Y中的一个区域内时,决定所有4位以获得其软判决值= 0或7.当接收到的符号位于区域B,C, D,F,J,K,0,P,T,V,W和X,3位决定为最可靠,以获得其软判决值= 0或7.对于剩余的1位, 通过在I或Q轴方向上的软判定来获得值= 0至7。 可以提供可以在多级(幅度和/或相位)调制中实现软判决并且可以充分发挥最大似然编码的校正性能的软判决方法。

    Method for choosing coding schemes, mappings, and puncturing rates for
modulations/encoding systems
    108.
    发明授权
    Method for choosing coding schemes, mappings, and puncturing rates for modulations/encoding systems 失效
    用于选择调制/编码系统的编码方案,映射和打孔速率的方法

    公开(公告)号:US6101626A

    公开(公告)日:2000-08-08

    申请号:US18678

    申请日:1998-02-04

    摘要: The purpose of the present invention is to provide a method for choosing the coding schemes, mappings, and puncturing rates for a modulation/demodulation system which would allow the system to compensate for certain transformations of the code in a post-Viterbi step as opposed to pre-Viterbi. This would allow for faster and simpler decoding of a code. The method includes the steps of: choosing a coding scheme and puncturing rate; determining a code generator matrix using said coding scheme and puncturing rate; multiplying the code generator matrix by the transformation matrix by the code generator matrix's feedback free right inverse and seeing if the outcome is equal to the code generator matrix multiplied by the transform matrix; multiplying the error matrix by the code generator matrix's feedback free right inverse by the code generator matrix and seeing if the outcome is equal to the error matrix; repeating all the steps until a code generator matrix that satisfies said invariancy equations is found; and choosing a mapping scheme that takes advantage of the invariancy.

    摘要翻译: 本发明的目的是提供一种用于选择调制/解调系统的编码方案,映射和打孔速率的方法,该方法将允许系统在后维特比步骤中补偿代码的某些变换,而不是 维特比之前。 这将允许对代码进行更快更简单的解码。 该方法包括以下步骤:选择编码方案和打孔率; 使用所述编码方案和打孔率来确定代码生成器矩阵; 将代码生成矩阵乘以代码生成矩阵的反馈自由权反转,并且查看结果是否等于乘以变换矩阵的代码生成矩阵; 通过代码生成器矩阵将代码生成矩阵的反馈自由逆乘乘误差矩阵,并查看结果是否等于误差矩阵; 重复所有步骤,直到找到满足所述不变方程的代码生成器矩阵; 并选择利用不间断的映射方案。

    Punctured maximum transition run code, apparatus and method for
providing the same
    109.
    发明授权
    Punctured maximum transition run code, apparatus and method for providing the same 失效
    穿刺最大过渡运行代码,提供相同的设备和方法

    公开(公告)号:US6097321A

    公开(公告)日:2000-08-01

    申请号:US69822

    申请日:1998-04-30

    申请人: Necip Sayiner

    发明人: Necip Sayiner

    摘要: A punctured maximum transition run (PMTR) code includes transition-allowed bit slots and transition-disallowed bit slots. Each of the transition-allowed bit slots is a bit slot in which a bit representing a third consecutive transition of a logic signal can occur whereas each of the transition-disallowed bit slots is a bit slot in which a bit representing a third consecutive transition of a logic signal cannot occur. There are at least two transition-allowed bit slots which are adjacent to each other. The transition occurs from a high logic level to a low logic level, or from a low logic level to a high logic level.

    摘要翻译: 穿孔最大过渡运行(PMTR)代码包括转换允许位时隙和转换不允许的位时隙。 每个转换允许位时隙是一个位时隙,其中可以发生表示逻辑信号的第三个连续转换的位,而每个转换不允许的位时隙是一个位时隙,其中表示第 不能发生逻辑信号。 至少有两个彼此相邻的转换允许位时隙。 转换从高逻辑电平到低逻辑电平,或从低逻辑电平发生到高逻辑电平。