利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

3522 条记录 (耗时 0.081 秒)

    Preambles in OFDMA system
    102.
    发明授权
    Preambles in OFDMA system 有权

    公开(公告)号：US10212017B2

    公开(公告)日：2019-02-19

    申请号：US15823072

    申请日：2017-11-27

    申请人： APPLE INC.

    发明人： Jianglei Ma ,  Hang Zhang ,  Wen Tong ,  Ming Jia ,  Peiying Zhu ,  Mo-Han Fong

    IPC分类号： H04L27/26 ,  H04B7/02 ,  H04L5/00 ,  H04W24/02 ,  H04B7/0452 ,  H04L7/04

    摘要： The present invention provides a preamble that is inserted into an OFDMA frame and has a common sequence for all the base stations participating in a transmission. The subscriber station performs fine synchronization using the common sequence on the common preamble, and the resulting peaks will provide the locations of candidate base stations. The base station specific search is then performed in the vicinities of those peaks by using base station specific pseudo-noise sequences. With this two stage cell search, the searching window is drastically reduced. The preamble is matched to known values by a respective receiver to decode the signals and permit multiple signals to be transferred from the transmitter to the receiver. The preamble may comprise two parts, Preamble-1 and Preamble-2, which may be used in different systems, including multioutput, multi-input (MIMO) systems.

    Semiconductor device
    103.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US10193717B2

    公开(公告)日：2019-01-29

    申请号：US15862929

    申请日：2018-01-05

    申请人： Kabushiki Kaisha Toshiba ,  Toshiba Electronic Devices & Storage Corporation

    发明人： Toshiyuki Yamagishi ,  Tomoya Horiguchi

    IPC分类号： H04L27/10 ,  H04L25/49 ,  H04L7/04 ,  H03M5/12 ,  G06E1/02 ,  G02B6/293 ,  H04L27/20

    摘要： A semiconductor device of an embodiment includes first and second couplers, an encoding circuit, and a demodulating circuit. The encoding circuit executes differential Manchester encoding on digital data based on a clock inputted thereto via the first coupler and outputs an encoded data. The demodulating circuit includes a first sampling circuit which samples the encoded data inputted via the second coupler based on a sampling frequency set to be two times higher than that of the encoded data and which outputs first sample data, a second sampling circuit which samples the encoded data at a timing earlier than that in the first sampling circuit and which outputs second sample data, a determination circuit which determines whether or not the first and the second sample data match each other, and a selection circuit which selects first phase data or second phase data from the first sample data.

    Distributing coherent signals to large electrical distances over serial interconnections
    104.
    发明授权
    Distributing coherent signals to large electrical distances over serial interconnections 有权

    公开(公告)号：US10181943B2

    公开(公告)日：2019-01-15

    申请号：US15486675

    申请日：2017-04-13

    申请人： Blue Danube Systems, Inc.

    发明人： Robert C. Frye ,  Mihai Banu

    IPC分类号： G01S7/40 ,  H01Q3/00 ,  H04B1/18 ,  H04L1/24 ,  H04L7/04 ,  H04B17/00 ,  H04L12/40

    摘要： A method involving a serial interconnection system having a first node, a second node, a plurality of calibration nodes that are electrically connected in series by the serial interconnection system, and a plurality of connection nodes corresponding to the plurality of serially connected calibration nodes and electrically connected in series by the serial interconnection system, the method involving: for each of the plurality of calibration nodes performing a measurement procedure involving: injecting a corresponding reference signal into that calibration node; and while the corresponding reference signal is being injected into that calibration node, determining a summation of the phases of signals appearing at the first and second nodes; from the determined phase summations for the plurality of calibration nodes, computing phase corrections for each of the plurality of calibration nodes; and applying the phase corrections to the corresponding plurality of connection nodes.

    Device for generating transmission clock of sink and transmission method using generated transmission clock
    106.
    发明授权
    Device for generating transmission clock of sink and transmission method using generated transmission clock 有权

    公开(公告)号：US10164767B2

    公开(公告)日：2018-12-25

    申请号：US15028601

    申请日：2014-08-26

    申请人： Doestek

    发明人： Tae Jin Kim ,  Dae Jung Shin

    IPC分类号： H04L7/02 ,  G06F1/04 ,  H04B1/40 ,  H04L7/04 ,  H04L7/00 ,  H04L7/033

    摘要： A semiconductor device for generating a transmission clock in a sink without a reference clock and a method of transmitting data from the sink to a source by use of the generated transmission clock are provided. The sink may include: a receiver configured to generate a digital control oscillator code by using a phase difference between a reception clock of a data signal received from a source and a recovered clock and configured to recover data from the data signal by using the recovered clock recovered by the generated digital control oscillator code; and a transmitter configured to generate a transmission clock by the digital control oscillator code having the recovered clock locked to the reception clock and configured to transmit return data to the source by using the transmission clock when a return data request identifier is received from the source.

    Receiving device and receiving method, and transmitting/receiving system
    108.
    发明授权
    Receiving device and receiving method, and transmitting/receiving system 有权

    公开(公告)号：US10148474B2

    公开(公告)日：2018-12-04

    申请号：US15513889

    申请日：2015-07-31

    申请人： Mitsubishi Electric Corporation

    发明人： Aki Kaizu ,  Masataka Imao ,  Eiji Matsuo

    IPC分类号： H04L27/22 ,  H04L25/49 ,  H03L7/08 ,  H04B1/00 ,  H04L7/00 ,  H04L7/04

    摘要： A receiving device includes: a receiver that receives a signal including PPM symbols; a clock generator that generates a clock for sampling; an A/D converter that digital-converts the received signal; a reference position detector that detects a leading position of the PPM symbols based on data from the A/D converter; and a clock error detector that detects a clock error. The clock error detector includes: a pulse position detector that detects a pulse position in the PPM symbols based on data from the reference position detector and A/D converter; a position error calculator that calculates a deviation of the pulse position based on data from the reference position detector, A/D converter, and pulse position detector; and a clock error calculator that calculates the clock error based on data from the position error calculator. The receiving device varies a frequency of the clock based on data from the clock error calculator.

    Method and apparatus for exchanging data between devices operating at different clock rates
    109.
    发明授权
    Method and apparatus for exchanging data between devices operating at different clock rates 有权

    公开(公告)号：US10133301B2

    公开(公告)日：2018-11-20

    申请号：US15348033

    申请日：2016-11-10

    申请人： Coriant Operations, Inc.

    发明人： John M. Golding

    IPC分类号： G06F1/12 ,  H03L7/08 ,  H04L7/00 ,  H04L7/10 ,  H04L7/04

    摘要： Source-synchronous communications between networked devices can be hindered by differing clock rates and data interface formats among the devices. By implementing a plurality of clock converters, a data interface format of a transmitting device is converted to a data interface format compatible with a receiving device. The clock converters provide a clock signal based on the source-synchronous data clock, and having a phase controlled with respect to an associated data signal. As a result, data exchange between devices operating at different clock rates is made possible.

    PHASE CALIBRATION METHOD AND ASSOCIATED PHASE LOCKED LOOP CIRCUIT
    110.
    发明申请
    PHASE CALIBRATION METHOD AND ASSOCIATED PHASE LOCKED LOOP CIRCUIT 审中-公开

    公开(公告)号：US20180294947A1

    公开(公告)日：2018-10-11

    申请号：US15690834

    申请日：2017-08-30

    申请人： MStar Semiconductor, Inc.

    发明人： Ting-Nan CHO ,  Kai-Wen CHENG ,  Tai-Lai TUNG

    IPC分类号： H04L7/033 ,  H04L7/04 ,  H03L7/08

    摘要： A phase calibration method for a phase locked loop (PLL) circuit in a wireless communication device includes: calculating a header phase error of a header sub-frame of a frame in an input signal and a pilot phase error of a pilot sub-frame of the frame, wherein the header sub-frame and the pilot sub-frame are known data; generating an estimated phase error according to a relationship between the header phase error and the pilot phase error; generating a phase compensating signal according to the estimated phase error and a filtered signal; adjusting the input signal according to the phase compensating signal to generate a compensated input signal; detecting a phase error between a data sub-frame corresponding to the pilot sub-frame in the compensated input signal and a reference signal; and generating the filtered signal according to the phase error.