公开(公告)号：US07406581B2

公开(公告)日：2008-07-29

申请号：US10830717

申请日：2004-04-23

Applicant: Trevor Southwell

Inventor： Trevor Southwell

IPC: G06F12/14

CPC classification number: G06F12/145 ,  G06F9/3842 ,  G06F9/3861 ,  G06F12/1441

Abstract: A method and system for validating speculative load operations. The system identifies speculative load operations that might be executed in a code sequence and after translating the virtual address of the speculative load to a physical address, a speculative load control unit is used to define a plurality of memory regions and has means for checking whether the physical addresses lie within at least one of said defined memory regions. In this way, the control unit allows the mapping of large physical page size to RAM devices and the extra address space is filtered off by the control unit so that speculative loads are not carried out in unknown regions.

Abstract translation: 一种用于验证投机负载操作的方法和系统。 该系统识别可能在代码序列中执行的推测加载操作，并且在将推测负载的虚拟地址转换为物理地址之后，推测负载控制单元用于定义多个存储器区域，并且具有用于检查是否 物理地址位于所述定义的存储区域的至少一个内。 以这种方式，控制单元允许将大的物理页面大小映射到RAM设备，并且由控制单元滤除额外的地址空间，以便在未知区域中不执行推测负载。

公开(公告)号：US07398440B2

公开(公告)日：2008-07-08

申请号：US11015748

申请日：2004-12-17

Applicant: Robert Warren

Inventor： Robert Warren

IPC: G01R31/28

CPC classification number: G01R31/318536 ,  G01R31/318563

Abstract: An integrated circuit comprising: a plurality of portions, each portion including test control circuitry; at least one test input arranged to receive test signals; and a multiplexer between the at least one test input and the test control circuitry, the multiplexer having a least one control input whereby the multiplexer is controllable to direct test signals to one of the plurality of portions.

Abstract translation: 一种集成电路，包括：多个部分，每个部分包括测试控制电路; 至少一个测试输入被布置成接收测试信号; 以及在所述至少一个测试输入和所述测试控制电路之间的多路复用器，所述多路复用器具有至少一个控制输入，由此所述多路复用器被控制以将测试信号引导到所述多个部分中的一个。

公开(公告)号：US07299462B2

公开(公告)日：2007-11-20

申请号：US09850666

申请日：2001-05-07

Applicant: Richard Shann ,  Stephen Jones

Inventor： Richard Shann ,  Stephen Jones

IPC: G06F9/45 ,  G06F9/44

CPC classification number: G06F9/44521

Abstract: A method of preparing an executable program from a plurality of object code modules, at least one of said object code modules including section data specifying a plurality of functions associated with relocation instructions, at least some of which functions are called in the executable program. The method comprises the steps of assigning an attribute to each function, said attribute being capable of providing an indication of whether the function is reachable, reading the section data and relocation instructions to ascertain if the function is called and setting the attribute to indicate the called status and preparing the executable program to only include functions with an indicated called status of reachable. A linker is provided for preparing the executable program from object code modules containing the relocation instructions. A computer program is provided to control the linker.

Abstract translation: 一种从多个目标代码模块准备可执行程序的方法，所述目标代码模块中的至少一个包括指定与重定位指令相关联的多个功能的部分数据，至少一些功能在可执行程序中被调用。 该方法包括以下步骤：将属性分配给每个功能，所述属性能够提供该功能是否可达的指示，读取部分数据和重定位指令以确定该功能是否被调用，并且设置该属性以指示被叫 状态并准备可执行程序，仅包括具有指定的可访问状态的功能。 提供了一个链接器，用于从包含重定位指令的目标代码模块中准备可执行程序。 提供计算机程序来控制连接器。

公开(公告)号：US07248602B2

公开(公告)日：2007-07-24

申请号：US10421317

申请日：2003-04-22

Applicant: William Robbins ,  David Wilkins

Inventor： William Robbins ,  David Wilkins

IPC: H04J3/16

CPC classification number: H04N21/434

Abstract: A circuit and method for demultiplexing in a receiver a digital data stream including at least two types of data. In one particular application, such a receiver is used in a television system having a digital set-top-box receiver. A first control circuit extracts a packet identifier from an input data packet in the digital data stream, and generates a signal in dependence on whether the input data packet is of the first or second type. Sets of information associated with the first types of data packets and required by the receiver are stored in a memory under the control of a second control circuit. A third control circuit, responsive to receipt of the first type of input data packet, determines whether at least part of the input data packet matches the stored sets of information, and sets a match signal responsive thereto.

Abstract translation: 一种用于在接收机中解复用包括至少两种类型的数据的数字数据流的电路和方法。 在一个特定应用中，这种接收机用在具有数字机顶盒接收机的电视系统中。 第一控制电路从数字数据流中的输入数据包中提取分组标识符，并根据输入数据分组是第一类还是第二类产生信号。 在第二控制电路的控制下，与第一类型的数据分组相关联并且由接收机所要求的信息集存储在存储器中。 响应于接收到第一类型的输入数据分组的第三控制电路确定输入数据分组的至少一部分是否与存储的信息组匹配，并且响应于此设置匹配信号。

公开(公告)号：US07243202B2

公开(公告)日：2007-07-10

申请号：US10107602

申请日：2002-03-27

Applicant: Tom Thomas

Inventor： Tom Thomas

IPC: G06F12/06 ,  H04L29/06

CPC classification number: H04L63/0428 ,  H04L45/742

Abstract: A method of locating packet identifiers held in respective memory locations in a memory, the method comprising receiving a plurality of packets, each packet including a packet identifier, searching said memory locations in a sequence to compare an incoming packet identifier with packet identifiers stored in the memory until a match is found, incrementing one of a set of counters associated respectively with the memory locations, said incremented counter being the one associated with the memory location where the match packet identifier is held, and reading values of each of the counters and using said values to determine the sequence in which the memory locations are searched for subsequent incoming packet identifiers.

Abstract translation: 一种定位保存在存储器中的相应存储器位置中的分组标识符的方法，所述方法包括接收多个分组，每个分组包括分组标识符，在序列中搜索所述存储器位置，以将输入分组标识符与存储在 存储器，直到找到匹配，递增与存储器位置相关联的一组计数器中的一个计数器，所述递增计数器是与保持匹配分组标识符的存储器位置相关联的计数器，以及每个计数器的读取值并使用 所述值用于确定搜索存储器位置以用于后续传入分组标识符的顺序。

公开(公告)号：US20070124811A1

公开(公告)日：2007-05-31

申请号：US11523775

申请日：2006-09-18

Applicant: Andrew Dellow ,  Peter Bennett ,  Rodrigo Cordero

Inventor： Andrew Dellow ,  Peter Bennett ,  Rodrigo Cordero

IPC: G06K9/00

CPC classification number: H04N7/162 ,  G06F12/1408 ,  H04H60/23 ,  H04N7/1675

Abstract: A memory stores data in an encrypted form. A modifiable register stores a memory address, a0, defining a boundary separating the memory into two regions. The lower region stores data encrypted using a key B, and the upper region stores data encrypted using a different key A. Data stored on the boundary address is encrypted using key A. Accordingly, when data is read from a memory address a, key A is used to decrypt the data if a≧a0, and key B is used if a

Abstract translation: 内存以加密形式存储数据。 可修改的寄存器存储一个存储器地址，即定义将存储器分隔成两个区域的边界的<0> 。 下部区域存储使用密钥B加密的数据，上部区域存储使用不同的密钥A加密的数据。使用密钥A对存储在边界地址上的数据进行加密。因此，当从存储器地址a读取数据时，密钥A 用于解密数据，如果> = a> 0 ，并且如果 0 使用键B。 然而，当数据被写入存储器地址a时，如果a> = a <0> +1，则使用密钥A来加密数据，如果A / SUB> +1。 当数据被写入边界地址时，<0> ，使边界的位置增加一个单位。

公开(公告)号：US20070067621A1

公开(公告)日：2007-03-22

申请号：US11522118

申请日：2006-09-15

Applicant: Andrew Dellow

Inventor： Andrew Dellow

IPC: H04L9/00

CPC classification number: H04N21/462 ,  H04N5/76 ,  H04N5/913 ,  H04N21/4334 ,  H04N21/434 ,  H04N21/4408 ,  H04N2005/91364

Abstract: A device for locating a DES key value that corresponds to a packet identification (PID) contained at a variable possible location which comprises part only of a 32-bit packet header. A table stored in memory contains for each DES key: (i) a packet header having 32 bits with a PID of either 12, 9 or 8 bits contained at a defined location and with zero values elsewhere, and (ii) a mask value also having 32 bits with ones contained at the said defined location of the PID and zeros elsewhere. The table is divided into regions for respective packet format types. An incoming packet header at an input is combined with a first one of the mask values from the table to provide a combined value that consists of the value held in the input packet header at the defined location and zeros elsewhere. This combined value is compared with the corresponding packet header stored in the table. When they are not equal, the combining and comparison is repeated for the next row of the table. When they are equal, the corresponding DES key value is read from the table and provided as an output. The system can cope with variable PID formats within the packet header without alteration to the hardware but merely with re-programming of the table contents.

Abstract translation: 用于定位对应于包含在可变可能位置的分组标识（PID）的DES密钥值的设备，该可变位置仅包括32位分组报头的一部分。 存储在存储器中的表包含每个DES密钥：（i）具有32位的分组报头，其中包含在定义的位置处的12,9或8位的PID，并且在其他地方具有零值，以及（ii）掩码值 具有32位，其中包含在PID的所述定义的位置处，并且其他地方具有零。 该表被分成用于相应分组格式类型的区域。 在输入处的输入分组报头与表中的第一个掩码值组合，以提供组合值，该组合值由保存在定义位置的输入分组报头中的值和其他地方的零组成。 将该组合值与存储在表中的相应分组报头进行比较。 当它们不相等时，对于表的下一行重复组合和比较。 当它们相等时，从表中读取相应的DES密钥值作为输出。 该系统可以处理数据包头中的可变PID格式，而不会改变硬件，但只能对表内容进行重新编程。

公开(公告)号：US07159199B2

公开(公告)日：2007-01-02

申请号：US10816799

申请日：2004-04-02

Applicant: Robert Warren

Inventor： Robert Warren

IPC: G06F17/50

CPC classification number: G06F17/5031

Abstract: The present invention is directed to methods for verifying adequate synchronization of signals that cross clock environments. According to one exemplary method, a circuit under design includes a plurality of functional elements and a plurality of clock environments, and has one or more signals passing from one clock environment to another therein. The method includes the steps of (i) modelling at least one of the functional elements to have an unknown state as an output for a predetermined time after a timing event of a clock signal, (ii) simulating the circuit, and (iii) determining which functional element is a synchronizer to thereby identify if there is a synchronization problem for a signal passing from one clock environment to another.

Abstract translation: 本发明涉及用于验证跨时钟环境的信号的充分同步的方法。 根据一个示例性方法，设计中的电路包括多个功能元件和多个时钟环境，并且具有从一个时钟环境到另一个时钟环境的一个或多个信号。 该方法包括以下步骤：（i）在时钟信号的定时事件，（ii）模拟电路之后的预定时间内将功能元件中的至少一个功能元件建模为具有未知状态作为输出，以及（iii）确定 哪个功能元件是同步器，从而识别对于从一个时钟环境到另一个时钟环境的信号是否存在同步问题。

公开(公告)号：US20060125941A1

公开(公告)日：2006-06-15

申请号：US11273477

申请日：2005-11-14

Applicant: Donald Baxter

Inventor： Donald Baxter

IPC: H04N5/335

CPC classification number: H04N5/37455 ,  H04N5/3742

Abstract: The image sensor includes an array of pixels, each pixel having a photo-diode, for providing a pixel voltage, an analog-to-digital converter (ADC) operable to convert the pixel voltage to a digital value and a memory for storing the digital value. Read circuitry is included for reading out the digital values from the pixels of the array in a predetermined order. The image sensor may be configured such that a counter incorporates the memory, and the counter may be adapted to operate as a shift register. The counters of two or more pixels may be connected to form one or more chains such that digital values can be read out in a bit-serial manner.

Abstract translation: 图像传感器包括像素阵列，每个像素具有用于提供像素电压的光电二极管，可操作以将像素电压转换为数字值的模数转换器（ADC）和用于存储数字的存储器 值。 包括读取电路，用于以预定顺序从阵列的像素读出数字值。 图像传感器可以被配置为使得计数器包括存储器，并且计数器可以适于作为移位寄存器来操作。 可以连接两个或更多个像素的计数器以形成一个或多个链，使得可以以串行方式读出数字值。

公开(公告)号：US20060092049A1

公开(公告)日：2006-05-04

申请号：US11236306

申请日：2005-09-27

Applicant: Andrew Dellow

Inventor： Andrew Dellow

IPC: H03M7/00

CPC classification number: G06F21/79 ,  G11C16/22

Abstract: A set-top-box has on-chip OTP memory emulated using an external flash memory and a series of on-chip fuses. The external memory is comprised of one or more regions, each having its own unique region identification. Each on-chip fuse corresponds to one of the memory regions and comprises a component which can be caused to change to a particular (blown) state irreversibly. When data first needs to be written to a region of the external memory, the identification of that region is appended to the data itself together with a parity field and a validity field. The resultant data packet is then encrypted by a cryptographic circuit using a secret key unique to the set-top-box and the encrypted data packet is written to the specified region of the external memory. Then, the on-chip fuse corresponding to the region that has been written to is irreversibly blown, effectively locking that region.