公开(公告)号：US20080296725A1

公开(公告)日：2008-12-04

申请号：US11955399

申请日：2007-12-13

Applicant: Ching-Nan Hsiao ,  Chung-Lin Huang ,  Chen-Yu Tsai ,  Chung-Yuan Lee

Inventor： Ching-Nan Hsiao ,  Chung-Lin Huang ,  Chen-Yu Tsai ,  Chung-Yuan Lee

IPC: H01L23/00 ,  H01L21/76

CPC classification number: H01L21/823481 ,  H01L27/11521

Abstract: A semiconductor component includes a substrate, two isolation structures, a conductor pattern and a dielectric layer. The isolation structures are disposed in the substrate, and each of the isolation structures has protruding portions protruding from the surface of the substrate. A trench is formed between the protruding portions. The included angle formed by the sidewall of the protruding portion and the surface of the substrate is an obtuse angle. The conductor pattern is disposed in the trench and fills the trench up. The dielectric layer is disposed between the conductor pattern and the substrate.

Abstract translation: 半导体部件包括基板，两个隔离结构，导体图案和电介质层。 隔离结构设置在基板中，并且每个隔离结构具有从基板的表面突出的突出部分。 在突出部之间形成沟槽。 由突出部分的侧壁和基板的表面形成的夹角是钝角。 导体图案设置在沟槽中并将沟槽填满。 电介质层设置在导体图案和基板之间。

公开(公告)号：US06855966B2

公开(公告)日：2005-02-15

申请号：US10435416

申请日：2003-05-09

Applicant: Ying-Cheng Chuang ,  Chung-Lin Huang

Inventor： Ying-Cheng Chuang ,  Chung-Lin Huang

IPC: H01L21/8247 ,  H01L27/115 ,  H01L31/072 ,  H01L31/0328 ,  H01L31/0336 ,  H01L31/109

CPC classification number: H01L21/28273 ,  H01L27/115 ,  H01L27/11521

Abstract: A floating gate and a fabricating method of the same. A semiconductor substrate is provided. A gate dielectric layer and a conducting layer are sequentially formed on the semiconductor substrate. A patterned hard mask layer having an opening is formed on the conducting layer, wherein a portion of the conducting layer is exposed through the opening. A spacer is formed on the sidewall of the opening. The patterned hard mask layer is removed. A conducting spacer is formed on the sidewall of the spacer. The exposed conducting layer and the exposed gate dielectric layer are sequentially removed.

Abstract translation: 浮栅及其制造方法。 提供半导体衬底。 在半导体衬底上依次形成栅介电层和导电层。 在导电层上形成具有开口的图案化的硬掩模层，其中导电层的一部分通过开口露出。 间隔件形成在开口的侧壁上。 图案化的硬掩模层被去除。 导电间隔件形成在间隔件的侧壁上。 依次去除暴露的导电层和暴露的栅介质层。

公开(公告)号：US06770520B2

公开(公告)日：2004-08-03

申请号：US10436800

申请日：2003-05-13

Applicant: Ying-Cheng Chuang ,  Chung-Lin Huang ,  Chi-Hui Lin

Inventor： Ying-Cheng Chuang ,  Chung-Lin Huang ,  Chi-Hui Lin

IPC: H01L21337

CPC classification number: H01L29/66825 ,  H01L21/28273 ,  H01L29/42324

Abstract: A floating gate and fabrication method thereof. A semiconductor substrate is provided, on which a gate dielectric layer, a conducting layer, and a patterned hard mask layer are sequentially formed. The surface of the conducting layer is covered by the patterned hard mask layer to form a gate. The conducting layer is etched to a predetermined depth to form an indentation using the patterned hard mask layer as a mask. The conducting layer is oxidized to form an oxide layer on the surface of the conducting layer. The oxide layer and the conducting layer are etched to form multiple tips using the patterned hard mask layer as a mask.

Abstract translation: 浮栅及其制造方法。 提供半导体衬底，其上依次形成栅介电层，导电层和图案化的硬掩模层。 导电层的表面被图案化的硬掩模层覆盖以形成栅极。 使用图案化的硬掩模层作为掩模，将导电层蚀刻到预定深度以形成凹陷。 导电层被氧化以在导电层的表面上形成氧化物层。 使用图案化的硬掩模层作为掩模，蚀刻氧化物层和导电层以形成多个尖端。

公开(公告)号：US06518153B1

公开(公告)日：2003-02-11

申请号：US09562911

申请日：2000-05-02

Applicant: Chi-hui Lin ,  Chung Lin Huang

Inventor： Chi-hui Lin ,  Chung Lin Huang

IPC: H01L913205

CPC classification number: H01L29/66545 ,  H01L21/28061 ,  H01L27/10873 ,  H01L29/4941

Abstract: A method of making embedded DRAM devices having integrated therein a gate electrode of low sheet resistance satisfying the requirement of high performance logic circuitry is provided. The gate electrode on a semiconductor substrate comprises a gate oxide film, a polysilicon film, a metal, a lightly doped diffusion layer, silicon dioxide spacers, and a source/drain diffusion layer. The metal is planted in an opening, where a capped silicon nitride used to occupy, on top the polysilicon film.

Abstract translation: 提供一种制造嵌入式DRAM器件的方法，其中集成了满足高性能逻辑电路要求的低片电阻的栅电极。 半导体衬底上的栅电极包括栅极氧化膜，多晶硅膜，金属，轻掺杂扩散层，二氧化硅间隔物和源极/漏极扩散层。 将金属种植在开口中，其中用于在多晶硅膜顶部占据的封盖氮化硅。