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    APPARATUS AND METHOD FOR ENCODING/DECODING DATA IN MULTIPLE ANTENNA COMMUNICATION SYSTEM
    111.
    发明申请
    APPARATUS AND METHOD FOR ENCODING/DECODING DATA IN MULTIPLE ANTENNA COMMUNICATION SYSTEM 审中-公开
    用于在多个天线通信系统中编码/解码数据的装置和方法

    公开(公告)号：US20080080642A1

    公开(公告)日：2008-04-03

    申请号：US11864444

    申请日：2007-09-28

    Applicant: Jong-Ho LEE ,  Sang-Boh YUN ,  Dae-Young PARK ,  Joo-Hyun LEE

    Inventor： Jong-Ho LEE ,  Sang-Boh YUN ,  Dae-Young PARK ,  Joo-Hyun LEE

    IPC: H04L27/00

    CPC classification number: H04L1/0643 ,  H04B7/0669

    Abstract: A data encoding/decoding method in a multiple antenna communication system is provided. In the multiple antenna communication system, a transmitting end includes an encoder for performing Space Time Block Code (STBC) encoding on certain symbols among Transmit (Tx) symbols, a multiplexer for performing spatial multiplexing on the rest of symbols among the Tx symbols, and a transmitter for transmitting the STBC encoded symbols and the spatial-multiplexed symbols through a plurality of antennas.

    Abstract translation: 提供了一种多天线通信系统中的数据编码/解码方法。 在多天线通信系统中，发送端包括：编码器，用于对发送（Tx）符号中的某些符号执行空时分组码（STBC）编码;多路复用器，用于对Tx符号之间的其余符号执行空间复用;以及 用于通过多个天线发送STBC编码符号和空间复用符号的发射机。

    Method of fabricating semiconductor device
    113.
    发明授权
    Method of fabricating semiconductor device 有权
    制造半导体器件的方法

    公开(公告)号：US07323419B2

    公开(公告)日：2008-01-29

    申请号：US11338633

    申请日：2006-01-25

    Applicant: Hyung-suk Jung ,  Jong-ho Lee ,  Jae-eon Park ,  Sung-kee Han ,  Min-joo Kim

    Inventor： Hyung-suk Jung ,  Jong-ho Lee ,  Jae-eon Park ,  Sung-kee Han ,  Min-joo Kim

    IPC: H01L22/302

    CPC classification number: H01L29/517 ,  H01L21/02172 ,  H01L21/265 ,  H01L21/28194 ,  H01L21/31691 ,  H01L21/32134 ,  H01L21/32135

    Abstract: A method of fabricating a semiconductor device including a high-k dielectric for as a gate insulating layer is provided. The method includes forming a high-k dielectric layer and a conductive layer on a substrate, dry etching a portion of the conductive layer, performing a process to increase a wet etch rate of a remaining portion of the conductive layer, and forming a conductive layer pattern by wet etching the remaining portion of the conductive layer after performing the plasma process or the ion implantation. The process to increase the wet etch rate of the conductive layer including a plasma process and/or an ion implantation on the remaining portion of the conductive layer.

    Abstract translation: 提供一种制造包括用作栅极绝缘层的高k电介质的半导体器件的方法。 该方法包括在衬底上形成高k电介质层和导电层，干蚀刻导电层的一部分，执行增加导电层剩余部分的湿蚀刻速率的工艺，以及形成导电层 在执行等离子体处理或离子注入之后湿式蚀刻导电层的剩余部分的图案。 包括在导电层的剩余部分上包括等离子体工艺和/或离子注入的导电层的湿蚀刻速率的方法。

    METHOD OF MANUFACTURING VERTICAL GALLIUM NITRIDE-BASED LIGHT EMITTING DIODE
    114.
    发明申请
    METHOD OF MANUFACTURING VERTICAL GALLIUM NITRIDE-BASED LIGHT EMITTING DIODE 失效
    制造立式氮化镓发光二极管的方法

    公开(公告)号：US20070264733A1

    公开(公告)日：2007-11-15

    申请号：US11697537

    申请日：2007-04-06

    Applicant: Pun Jae CHOI ,  Jong Ho LEE

    Inventor： Pun Jae CHOI ,  Jong Ho LEE

    IPC: H01L21/00

    CPC classification number: H01L33/0079 ,  H01L33/0075 ,  H01L33/22

    Abstract: A method of manufacturing a vertical GaN-based LED comprises preparing an n-type GaN substrate; sequentially forming an active layer and a p-type nitride semiconductor layer on the n-type GaN substrate through an epitaxial growth method; forming a p-electrode on the p-type nitride semiconductor layer; wet-etching the lower surface of the n-type GaN substrate so as to reduce the thickness of the n-type GaN substrate; forming a flat n-type bonding pad on the wet-etched lower surface of the n-type GaN substrate, the n-type bonding pad defining an n-electrode formation region; and forming an n-electrode on the n-type bonding pad.

    Abstract translation: 制造垂直GaN基LED的方法包括制备n型GaN衬底; 通过外延生长法在n型GaN衬底上依次形成有源层和p型氮化物半导体层; 在p型氮化物半导体层上形成p电极; 湿式蚀刻n型GaN衬底的下表面以减小n型GaN衬底的厚度; 在n型GaN衬底的湿蚀刻下表面上形成平坦的n型焊盘，n型焊盘限定n电极形成区域; 在n型接合焊盘上形成n电极。

    Semiconductor devices having different gate dielectric layers and methods of manufacturing the same
    120.
    发明申请
    Semiconductor devices having different gate dielectric layers and methods of manufacturing the same 审中-公开
    具有不同栅介质层的半导体器件及其制造方法

    公开(公告)号：US20070023842A1

    公开(公告)日：2007-02-01

    申请号：US11432717

    申请日：2006-05-12

    Applicant: Hyung-suk Jung ,  Jong-ho Lee ,  Ha-jin Lim ,  Yun-seok Kim

    Inventor： Hyung-suk Jung ,  Jong-ho Lee ,  Ha-jin Lim ,  Yun-seok Kim

    IPC: H01L29/94 ,  H01L29/768 ,  H01L21/8238

    CPC classification number: H01L21/823857 ,  H01L21/28088 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/3142 ,  H01L21/31645 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517

    Abstract: A first transistor includes a first channel region of a first conductivity type located at a first surface region of a semiconductor substrate, a first gate dielectric which includes a first HfO2 layer located over the first channel region, and a first gate located over the first gate dielectric. The first gate includes a first polysilicon layer doped with an impurity of the first conductivity type. The second transistor includes a second channel region of a second conductivity type located at a second surface region of the semiconductor substrate, a second gate dielectric which includes a second HfO2 layer and an Al2O3 layer located over the second channel region, and a second gate located over the second gate dielectric. The second gate includes a second polysilicon layer doped with an impurity of the second conductivity type, and the second conductivity type is opposite the first conductivity type.

    Abstract translation: 第一晶体管包括位于半导体衬底的第一表面区域处的第一导电类型的第一沟道区，包括位于第一沟道区上方的第一HfO 2层的第一栅极电介质，以及 位于第一栅极电介质上方的第一栅极。 第一栅极包括掺杂有第一导电类型的杂质的第一多晶硅层。 第二晶体管包括位于半导体衬底的第二表面区域处的第二导电类型的第二沟道区，包括第二HfO 2层和Al 2 O 2层的第二栅极电介质， 位于第二沟道区上方的第二栅极和位于第二栅极电介质上方的第二栅极。 第二栅极包括掺杂有第二导电类型的杂质的第二多晶硅层，第二导电类型与第一导电类型相反。

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