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    Method of fabricating semiconductor device
    1.
    发明授权
    Method of fabricating semiconductor device 有权
    制造半导体器件的方法

    公开(公告)号：US07323419B2

    公开(公告)日：2008-01-29

    申请号：US11338633

    申请日：2006-01-25

    申请人： Hyung-suk Jung ,  Jong-ho Lee ,  Jae-eon Park ,  Sung-kee Han ,  Min-joo Kim

    发明人： Hyung-suk Jung ,  Jong-ho Lee ,  Jae-eon Park ,  Sung-kee Han ,  Min-joo Kim

    IPC分类号： H01L22/302

    CPC分类号： H01L29/517 ,  H01L21/02172 ,  H01L21/265 ,  H01L21/28194 ,  H01L21/31691 ,  H01L21/32134 ,  H01L21/32135

    摘要： A method of fabricating a semiconductor device including a high-k dielectric for as a gate insulating layer is provided. The method includes forming a high-k dielectric layer and a conductive layer on a substrate, dry etching a portion of the conductive layer, performing a process to increase a wet etch rate of a remaining portion of the conductive layer, and forming a conductive layer pattern by wet etching the remaining portion of the conductive layer after performing the plasma process or the ion implantation. The process to increase the wet etch rate of the conductive layer including a plasma process and/or an ion implantation on the remaining portion of the conductive layer.

    摘要翻译： 提供一种制造包括用作栅极绝缘层的高k电介质的半导体器件的方法。 该方法包括在衬底上形成高k电介质层和导电层，干蚀刻导电层的一部分，执行增加导电层剩余部分的湿蚀刻速率的工艺，以及形成导电层 在执行等离子体处理或离子注入之后湿式蚀刻导电层的剩余部分的图案。 包括在导电层的剩余部分上包括等离子体工艺和/或离子注入的导电层的湿蚀刻速率的方法。

    Method of fabricating semiconductor device
    2.
    发明申请
    Method of fabricating semiconductor device 有权
    制造半导体器件的方法

    公开(公告)号：US20060175289A1

    公开(公告)日：2006-08-10

    申请号：US11338633

    申请日：2006-01-25

    申请人： Hyung-suk Jung ,  Jong-ho Lee ,  Jae-eon Park ,  Sung-kee Han ,  Min-joo Kim

    发明人： Hyung-suk Jung ,  Jong-ho Lee ,  Jae-eon Park ,  Sung-kee Han ,  Min-joo Kim

    IPC分类号： C03C15/00 ,  H01L21/302 ,  B44C1/22 ,  C23F1/00

    CPC分类号： H01L29/517 ,  H01L21/02172 ,  H01L21/265 ,  H01L21/28194 ,  H01L21/31691 ,  H01L21/32134 ,  H01L21/32135

    摘要： A method of fabricating a semiconductor device including a high-k dielectric for as a gate insulating layer is provided. The method includes forming a high-k dielectric layer and a conductive layer on a substrate, dry etching a portion of the conductive layer, performing a process to increase a wet etch rate of a remaining portion of the conductive layer, and forming a conductive layer pattern by wet etching the remaining portion of the conductive layer after performing the plasma process or the ion implantation. The process to increase the wet etch rate of the conductive layer including a plasma process and/or an ion implantation on the remaining portion of the conductive layer.

    摘要翻译： 提供一种制造包括用作栅极绝缘层的高k电介质的半导体器件的方法。 该方法包括在衬底上形成高k电介质层和导电层，干蚀刻导电层的一部分，执行增加导电层剩余部分的湿蚀刻速率的工艺，以及形成导电层 在执行等离子体处理或离子注入之后湿式蚀刻导电层的剩余部分的图案。 包括在导电层的剩余部分上包括等离子体工艺和/或离子注入的导电层的湿蚀刻速率的方法。

    Method of fabricating gate of semiconductor device using oxygen-free ashing process
    3.
    发明申请
    Method of fabricating gate of semiconductor device using oxygen-free ashing process 审中-公开
    使用无氧灰化工艺制造半导体器件栅极的方法

    公开(公告)号：US20070178637A1

    公开(公告)日：2007-08-02

    申请号：US11699784

    申请日：2007-01-30

    申请人： Hyung-suk Jung ,  Cheol-kyu Lee ,  Jong-ho Lee ,  Sung-kee Han ,  Yun-seok Kim

    发明人： Hyung-suk Jung ,  Cheol-kyu Lee ,  Jong-ho Lee ,  Sung-kee Han ,  Yun-seok Kim

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/823857 ,  H01L21/823842

    摘要： A method of fabricating a gate of a semiconductor device using an oxygen-free ashing process is disclosed. The method includes forming a high-k dielectric film, having a dielectric constant higher than a silicon oxide film, on a semiconductor substrate including an NMOS region and a PMOS region, forming an etching target film on the high-k dielectric film, forming a photoresist pattern to expose any one region of the two regions, on the etching target film, etching the etching target film using the photoresist pattern as an etching mask, and removing the photoresist pattern using plasma formed in the presence of an oxygen-free reactive gas.

    摘要翻译： 公开了一种使用无氧灰化工艺制造半导体器件的栅极的方法。 该方法包括在包括NMOS区域和PMOS区域的半导体衬底上形成具有高于氧化硅膜的介电常数的高k电介质膜，在高k电介质膜上形成蚀刻靶膜，形成 光致抗蚀剂图案以暴露两个区域的任何一个区域，在蚀刻目标膜上，使用光刻胶图案蚀刻蚀刻目标膜作为蚀刻掩模，以及使用在无氧反应气体存在下形成的等离子体去除光致抗蚀剂图案 。

    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
    5.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开
    半导体器件及其制造方法

    公开(公告)号：US20080079086A1

    公开(公告)日：2008-04-03

    申请号：US11831069

    申请日：2007-07-31

    申请人： Hyung-suk Jung ,  Jong-ho Lee ,  Sung-kee Han ,  Ho Lee ,  Ha-jin Lim

    发明人： Hyung-suk Jung ,  Jong-ho Lee ,  Sung-kee Han ,  Ho Lee ,  Ha-jin Lim

    IPC分类号： H01L21/336 ,  H01L27/085

    CPC分类号： H01L21/823807

    摘要： A semiconductor device and a method of manufacturing the semiconductor device, in which the semiconductor device includes a semiconductor substrate in which PMOS transistor regions and NMOS transistor regions are formed, a PMOS transistor including P-type source and drain regions and a gate electrode, and an NMOS transistor formed on an Si channel region between N-type source and drain regions. The PMOS transistor is formed in each PMOS transistor region, and the gate electrode is formed on a high-dielectric gate insulating film formed on an SiGe channel region between the P-type source and drain regions. Further, the NMOS transistor includes a high-dielectric gate insulating film and a gate electrode formed on the gate insulating film, and the NMOS transistor is formed in each NMOS transistor region.

    摘要翻译： 一种半导体器件和半导体器件的制造方法，其中半导体器件包括其中形成有PMOS晶体管区域和NMOS晶体管区域的半导体衬底，包括P型源极和漏极区域的PMOS晶体管和栅极电极，以及 形成在N型源区和漏区之间的Si沟道区上的NMOS晶体管。 PMOS晶体管形成在每个PMOS晶体管区域中，并且栅电极形成在形成在P型源区和漏区之间的SiGe沟道区上的高电介质栅极绝缘膜上。 此外，NMOS晶体管包括高电介质栅极绝缘膜和形成在栅极绝缘膜上的栅电极，并且NMOS晶体管形成在每个NMOS晶体管区域中。

    Semiconductor devices having different gate dielectric layers and methods of manufacturing the same
    8.
    发明申请
    Semiconductor devices having different gate dielectric layers and methods of manufacturing the same 审中-公开
    具有不同栅介质层的半导体器件及其制造方法

    公开(公告)号：US20070023842A1

    公开(公告)日：2007-02-01

    申请号：US11432717

    申请日：2006-05-12

    申请人： Hyung-suk Jung ,  Jong-ho Lee ,  Ha-jin Lim ,  Yun-seok Kim

    发明人： Hyung-suk Jung ,  Jong-ho Lee ,  Ha-jin Lim ,  Yun-seok Kim

    IPC分类号： H01L29/94 ,  H01L29/768 ,  H01L21/8238

    CPC分类号： H01L21/823857 ,  H01L21/28088 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/3142 ,  H01L21/31645 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517

    摘要： A first transistor includes a first channel region of a first conductivity type located at a first surface region of a semiconductor substrate, a first gate dielectric which includes a first HfO2 layer located over the first channel region, and a first gate located over the first gate dielectric. The first gate includes a first polysilicon layer doped with an impurity of the first conductivity type. The second transistor includes a second channel region of a second conductivity type located at a second surface region of the semiconductor substrate, a second gate dielectric which includes a second HfO2 layer and an Al2O3 layer located over the second channel region, and a second gate located over the second gate dielectric. The second gate includes a second polysilicon layer doped with an impurity of the second conductivity type, and the second conductivity type is opposite the first conductivity type.

    摘要翻译： 第一晶体管包括位于半导体衬底的第一表面区域处的第一导电类型的第一沟道区，包括位于第一沟道区上方的第一HfO 2层的第一栅极电介质，以及 位于第一栅极电介质上方的第一栅极。 第一栅极包括掺杂有第一导电类型的杂质的第一多晶硅层。 第二晶体管包括位于半导体衬底的第二表面区域处的第二导电类型的第二沟道区，包括第二HfO 2层和Al 2 O 2层的第二栅极电介质， 位于第二沟道区上方的第二栅极和位于第二栅极电介质上方的第二栅极。 第二栅极包括掺杂有第二导电类型的杂质的第二多晶硅层，第二导电类型与第一导电类型相反。