LDO Regulator
    111.
    发明申请
    LDO Regulator 有权
    LDO调节器

    公开(公告)号:US20140247028A1

    公开(公告)日:2014-09-04

    申请号:US14350253

    申请日:2012-09-27

    Applicant: ST-Ericsson SA

    CPC classification number: G05F1/575 G05F1/10

    Abstract: The present invention concerns a low dropout (LDO) regulator of regulating an output signal, the LDO regulator comprising an input stage (15) and an output stage (17), the input stage being adapted to receive a reference signal (VREF) and a feed-back signal (VF) depending on an output signal (VOUT), and to output an intermediate signal based on the feedback signal and on the reference signal, wherein the LDO regulator further comprises a gain stage (16) having a given gain value, which is configurable and wherein the output signal is regulated based on the gain value of the gain stage and on the intermediate signal.

    Abstract translation: 本发明涉及调节输出信号的低压差(LDO)调节器,LDO调节器包括输入级(15)和输出级(17),输入级适于接收参考信号(VREF)和 根据输出信号(VOUT)反馈信号(VF),并且基于反馈信号和参考信号输出中间信号,其中LDO调节器还包括具有给定增益值的增益级(16) ,其是可配置的,并且其中基于增益级的增益值和中间信号来调节输出信号。

    Efficient Regulation of Capacitance Voltage(s) in a Switched Mode Multilevel Power Converter
    112.
    发明申请
    Efficient Regulation of Capacitance Voltage(s) in a Switched Mode Multilevel Power Converter 有权
    高效调节开关模式多电平转换器中的电容电压

    公开(公告)号:US20140232364A1

    公开(公告)日:2014-08-21

    申请号:US13963087

    申请日:2013-08-09

    Applicant: ST-Ericsson SA

    Abstract: A power conversion circuit uses smaller, cheaper, and faster analog and digital circuits, e.g., buffers, comparators, and processing circuits, to provide the information necessary to control a multilevel power converter faster, cheaper, and with a smaller footprint than conventional techniques. For example, a current detection circuit indirectly measures a direction of a current through an inductor connected between midpoint node and an output node of a multilevel power converter based on comparisons between voltages associated with the multilevel power converter. A capacitor voltage detection detects a capacitor voltage across the flying capacitor to generate a logic signal based on a comparison between the capacitor voltage and a first reference voltage. A control circuit selects an operating state of the multilevel power converter to regulate a first capacitor voltage across the first capacitor based on the indirectly measured direction of the inductor current, the logic signal, and an input command signal.

    Abstract translation: 功率转换电路使用更小,更便宜和更快的模拟和数字电路,例如缓冲器,比较器和处理电路,以提供与传统技术相比更快,更便宜和更小占地面积来控制多电平功率转换器所需的信息。 例如,电流检测电路基于与多电平功率转换器相关联的电压的比较,间接地测量通过连接在多电平电力转换器的中点节点和输出节点之间的电感器的电流的方向。 电容器电压检测检测跨越飞行电容器的电容器电压,以基于电容器电压和第一参考电压之间的比较来产生逻辑信号。 控制电路基于间接测量的电感器电流方向,逻辑信号和输入命令信号,选择多电平电力转换器的工作状态来调节跨第一电容器的第一电容器电压。

    DCM and PFM Management
    113.
    发明申请
    DCM and PFM Management 审中-公开
    DCM和PFM管理

    公开(公告)号:US20140218117A1

    公开(公告)日:2014-08-07

    申请号:US14240477

    申请日:2012-08-14

    Applicant: ST-ERICSSON SA

    CPC classification number: H02M3/158 H02M3/156

    Abstract: The present invention relates to a voltage regulating device comprising a power stage (30) comprising an inductor (L) between a first node (P1) and a second node (P2); a first switch (A) between the first node (Pi) and a power supply node (P3) for which the potential (Vbat) is non-zero and of constant polarity; a first capacitor (CNEG) between a node (P5) at a reference potential and a second switch (B) coupled to the first node (P1); a second capacitor (CPOS) between a node (P7) at the reference potential and a third switch (C) coupled to the second node (P2); a fourth switch (D) between the second node (P2) and a node (P8) at the reference potential; a fifth switch (E) between the first node (P1 and a node (P9) at the reference potential; a first output (P4) for delivering a first voltage corresponding to the voltage at the terminals of the first capacitor (CNEG); a second output (P6) for delivering a second voltage corresponding to the voltage at the terminals of the second capacitor (CPOS); The power stage further comprises at least one comparator (40, 41) arranged to detect an inversion of the current in the inductor and the power stage is further arranged to close the fourth and fifth switches and to open the first, second and third switches upon detection of an inversion of the current in the inductor.

    Abstract translation: 电压调节装置技术领域本发明涉及一种电压调节装置,包括在第一节点(P1)和第二节点(P2)之间包括电感器(L)的功率级(30) 第一节点(Pi)和电位(Vbat)为非零且恒定极性的电源节点(P3)之间的第一开关(A) 在参考电位的节点(P5)与耦合到第一节点(P1)的第二开关(B)之间的第一电容器(CNEG); 在参考电位的节点(P7)和耦合到第二节点(P2)的第三开关(C)之间的第二电容器(CPOS); 在第二节点(P2)和参考电位的节点(P8)之间的第四开关(D) 在第一节点(P1和参考电位处的节点(P9)之间的第五开关(E);用于传送对应于第一电容器(CNEG)的端子处的电压的第一电压的第一输出(P4); 第二输出(P6),用于传送对应于在第二电容器(CPOS)的端子处的电压的第二电压;功率级还包括至少一个比较器(40,41),其被布置成检测电感器中的电流的反相 并且功率级还被布置成闭合第四和第五开关,并且在检测到电感器中的电流的反转时打开第一,第二和第三开关。

    Double output linearized low-noise charge pump with loop filter area reduction
    114.
    发明授权
    Double output linearized low-noise charge pump with loop filter area reduction 有权
    双路输出线性化低噪声电荷泵,减少环路滤波面积

    公开(公告)号:US08766683B2

    公开(公告)日:2014-07-01

    申请号:US13946411

    申请日:2013-07-19

    Applicant: ST-Ericsson SA

    CPC classification number: H03L7/0891 H03L7/0895 H03L7/093

    Abstract: According to embodiments, dual path loop filter circuits are described which have, for example, a single charge pump. The current flow in the DPLF circuit is architected to source, during an injection time period, a first current to the loop filter, sink, also during the injection time period, a second current from the loop filter, wherein the first current has a magnitude of α*I and the second current has a magnitude of β*I, and sink, during a linearization time period, a third current from the loop filter, wherein the third current has a magnitude of (α−β)*I.

    Abstract translation: 根据实施例,描述了具有例如单个电荷泵的双路径环路滤波器电路。 在DPLF电路中的电流流动被设计成在注入时间段期间将源自环路滤波器的第一电流源自环路滤波器,也可以在注入时间段期间从环路滤波器引出第二电流,其中第一电流具有幅度 并且所述第二电流具有大于所述环路滤波器的第三电流,并且在线性化时间段期间从所述环路滤波器吸收第三电流,其中所述第三电流的幅度为(α&bgr)* I 。

    METHOD OF SETTING UE MODE SWITCHING FOR RPD REDUCTION
    115.
    发明申请
    METHOD OF SETTING UE MODE SWITCHING FOR RPD REDUCTION 有权
    设置用于减少RPD的UE模式切换的方法

    公开(公告)号:US20140153456A1

    公开(公告)日:2014-06-05

    申请号:US13692782

    申请日:2012-12-03

    Applicant: ST-ERICSSON SA

    CPC classification number: H04W52/38 H04W52/223 H04W52/288 H04W52/325

    Abstract: A UE communication device is provided having a transmitter architecture that transmits SRS transmissions and PUSCH transmissions. A reference mode chosen from a LPM, an MPM and an HPM is selected based on a present power mode of the SRS transmission or based on a predicted power mode that the PUSCH transmission following the present SRS transmission will likely operate in. The transmitter architecture has an exemplary extended switching point structure allowing the RPD between the SRS transmission used for pre-quarter selection and the subsequent PUSCH transmission applying the pre-quarter to be minimized.

    Abstract translation: 提供具有发送SRS传输和PUSCH传输的发射机架构的UE通信设备。 从LPM,MPM和HPM选择的参考模式基于SRS传输的当前功率模式或者基于当前SRS传输之后的PUSCH传输将可能操作的预测功率模式来选择。发射机架构具有 允许用于前四分之一选择的SRS传输之间的RPD和应用前四分之一的后续PUSCH传输的示范性扩展切换点结构被最小化。

    Probability Calculation of RAT Candidate
    116.
    发明申请
    Probability Calculation of RAT Candidate 有权
    RAT候选者的概率计算

    公开(公告)号:US20140128091A1

    公开(公告)日:2014-05-08

    申请号:US14116523

    申请日:2012-04-24

    Applicant: ST-Ericsson SA

    Inventor: Bjorn Engström

    CPC classification number: H04W48/18 H04W88/06

    Abstract: An apparatus (200) for use in a telecommunications system. The apparatus (200) comprising a memory (240) and a controller (210). The controller (210) is configured to receive a radio frequency bandwidth and identify a first candidate carrier frequency (710) from the received a radio frequency bandwidth. The controller is further configured to, for a first potential radio access technology determine a probability estimate (Prob) for the first candidate carrier frequency (710) being a carrier frequency of the first potential radio access technology, where in the probability estimate is based on a received power in a transmission band of the first potential radio access technology having the candidate carrier frequency (710) and on a received power in a guard band of the first potential radio access technology having the candidate carrier frequency and from this select a radio access technology based on the probability estimate (Prob) for the candidate carrier frequency (710).

    Abstract translation: 一种用于电信系统的装置(200)。 装置(200)包括存储器(240)和控制器(210)。 控制器(210)被配置为从接收的射频带宽接收射频带宽并识别第一候选载波频率(710)。 控制器进一步被配置为,对于第一潜在无线电接入技术,确定作为第一潜在无线电接入技术的载波频率的第一候选载波频率(710)的概率估计(Prob),其中概率估计基于 具有候选载波频率(710)的第一潜在无线电接入技术的传输频带中的接收功率和具有候选载波频率的第一潜在无线电接入技术的保护频带中的接收功率,并且从其选择无线接入 基于候选载波频率的概率估计(Prob)的技术(710)。

    STANDING WAVE RATIO METER FOR INTEGRATED ANTENNA TUNER
    117.
    发明申请
    STANDING WAVE RATIO METER FOR INTEGRATED ANTENNA TUNER 有权
    用于集成天线调谐器的标准波比表

    公开(公告)号:US20140120849A1

    公开(公告)日:2014-05-01

    申请号:US13664014

    申请日:2012-10-30

    Applicant: ST-ERICSSON SA

    Abstract: The invention provides circuitry integrated into a silicon chip that measures aspects of an RF signal on a transmission line in order to provide data that is ultimately used by an antenna tuner circuit to substantially match the impedance of the antenna with that of the transmission line providing the RF frequency to be transmitted.

    Abstract translation: 本发明提供集成到硅芯片中的电路,其测量传输线上的RF信号的各方面,以便提供最终由天线调谐器电路使用的数据,以将天线的阻抗与传输线的阻抗基本匹配, RF频率要传输。

    Fully-Digital BIST for RF Receivers
    118.
    发明申请
    Fully-Digital BIST for RF Receivers 有权
    RF接收机的全数字BIST

    公开(公告)号:US20140092946A1

    公开(公告)日:2014-04-03

    申请号:US13629993

    申请日:2012-09-28

    Applicant: ST-ERICSSON SA

    CPC classification number: H04B17/004 H04B17/0085 H04B17/20 H04B17/29

    Abstract: A built-in receiver self-test system provides on-chip testing with minimal change to the receiver footprint. The system digitally generates a two-tone test signal, and tests the nonlinearities of the receiver using the generated two-tone test signal. To that end, the self-test system comprises a stimulus generator, a downconverter, and a demodulator, all of which are disposed on a common receiver chip. The stimulus generator generates a test signal comprising first and second tones at respective first and second frequencies, where the first and second frequencies are spaced by an offset frequency, and where the first frequency comprises a non-integer multiple of the offset frequency. The downcoverter downconverts the test signal to generate an In-phase component and a Quadrature component. The demodulator measures an amplitude of the intermodulation tone by demodulating the In-phase and Quadrature components based on a reference frequency.

    Abstract translation: 内置的接收机自检系统提供片上测试,对接收机的占位面积进行最小的改变。 该系统数字地产生双音测试信号,并使用生成的双音测试信号测试接收机的非线性。 为此,自检系统包括一个刺激发生器,一个下变频器和一个解调器,所有这些都设置在公共的接收芯片上。 刺激发生器产生测试信号,该测试信号包括相应的第一和第二频率处的第一和第二音调,其中第一和第二频率间隔偏移频率,并且其中第一频率包括偏移频率的非整数倍。 下变频器将测试信号下变频以产生同相分量和正交分量。 解调器通过基于参考频率解调同相和正交分量来测量互调音的幅度。

    DOUBLE OUTPUT LINEARIZED LOW-NOISE CHARGE PUMP WITH LOOP FILTER AREA REDUCTION
    119.
    发明申请
    DOUBLE OUTPUT LINEARIZED LOW-NOISE CHARGE PUMP WITH LOOP FILTER AREA REDUCTION 有权
    双输出线性低噪声充电泵,带环路滤波器区域减少

    公开(公告)号:US20140049304A1

    公开(公告)日:2014-02-20

    申请号:US13946411

    申请日:2013-07-19

    Applicant: ST-Ericsson SA

    CPC classification number: H03L7/0891 H03L7/0895 H03L7/093

    Abstract: According to embodiments, dual path loop filter circuits are described which have, for example, a single charge pump. The current flow in the DPLF circuit is architected to source, during an injection time period, a first current to the loop filter, sink, also during the injection time period, a second current from the loop filter, wherein the first current has a magnitude of α*I and the second current has a magnitude of β*I, and sink, during a linearization time period, a third current from the loop filter, wherein the third current has a magnitude of (α−β)*I.

    Abstract translation: 根据实施例,描述了具有例如单个电荷泵的双路径环路滤波器电路。 在DPLF电路中的电流流动被设计成在注入时间段期间将源自环路滤波器的第一电流源自环路滤波器,也可以在注入时间段期间从环路滤波器引出第二电流,其中第一电流具有幅度 并且第二电流具有β* I的大小,并且在线性化时间周期期间从环路滤波器吸收第三电流,其中第三电流具有(α-β)* I的量值。

    Current-Mode Controller for Step-Down (Buck) Converter
    120.
    发明申请
    Current-Mode Controller for Step-Down (Buck) Converter 有权
    降压(降压)转换器的电流模式控制器

    公开(公告)号:US20140049239A1

    公开(公告)日:2014-02-20

    申请号:US13935630

    申请日:2013-07-05

    Applicant: ST-Ericsson SA

    Inventor: Benoît Labbe

    CPC classification number: H02M3/156 H02M2001/0009 H02M2001/0025

    Abstract: A current-mode regulator relies on indirect current measurement to facilitate slope compensation used to stabilize the operation of a buck converter. The current-mode regulator comprises an inductor, a switching network, and a controller. The inductor delivers an output current to a load. The switching network selectively connects the inductor input to an input voltage or a second voltage. The regulator controls the switching network. An inner loop control circuit of the regulator comprises the switching network, a current measuring circuit, a slope circuit, a comparator, and a switching controller. The current measuring circuit comprises a passive network connected to the inductor input and operative to indicate an inductor current as a measurement voltage. The slope circuit applies a time-varying voltage having a positive slope to the measurement voltage. The comparator compares a slope compensated measurement voltage to the control voltage. The switching regulator controls the switching network in response to the output of the comparator.

    Abstract translation: 电流模式调节器依靠间接电流测量来促进用于稳定降压转换器运行的斜率补偿。 电流模式调节器包括电感器,开关网络和控制器。 电感器将负载输出电流。 开关网络选择性地将电感器输入端连接到输入电压或第二电压。 调节器控制开关网络。 调节器的内环控制电路包括开关网络,电流测量电路,斜坡电路,比较器和开关控制器。 电流测量电路包括连接到电感器输入的无源网络,并且用于将电感器电流指示为测量电压。 斜率电路对测量电压施加具有正斜率的时变电压。 比较器将斜率补偿测量电压与控制电压进行比较。 开关稳压器响应于比较器的输出控制开关网络。

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