Abstract:
The present invention concerns a low dropout (LDO) regulator of regulating an output signal, the LDO regulator comprising an input stage (15) and an output stage (17), the input stage being adapted to receive a reference signal (VREF) and a feed-back signal (VF) depending on an output signal (VOUT), and to output an intermediate signal based on the feedback signal and on the reference signal, wherein the LDO regulator further comprises a gain stage (16) having a given gain value, which is configurable and wherein the output signal is regulated based on the gain value of the gain stage and on the intermediate signal.
Abstract:
A power conversion circuit uses smaller, cheaper, and faster analog and digital circuits, e.g., buffers, comparators, and processing circuits, to provide the information necessary to control a multilevel power converter faster, cheaper, and with a smaller footprint than conventional techniques. For example, a current detection circuit indirectly measures a direction of a current through an inductor connected between midpoint node and an output node of a multilevel power converter based on comparisons between voltages associated with the multilevel power converter. A capacitor voltage detection detects a capacitor voltage across the flying capacitor to generate a logic signal based on a comparison between the capacitor voltage and a first reference voltage. A control circuit selects an operating state of the multilevel power converter to regulate a first capacitor voltage across the first capacitor based on the indirectly measured direction of the inductor current, the logic signal, and an input command signal.
Abstract:
The present invention relates to a voltage regulating device comprising a power stage (30) comprising an inductor (L) between a first node (P1) and a second node (P2); a first switch (A) between the first node (Pi) and a power supply node (P3) for which the potential (Vbat) is non-zero and of constant polarity; a first capacitor (CNEG) between a node (P5) at a reference potential and a second switch (B) coupled to the first node (P1); a second capacitor (CPOS) between a node (P7) at the reference potential and a third switch (C) coupled to the second node (P2); a fourth switch (D) between the second node (P2) and a node (P8) at the reference potential; a fifth switch (E) between the first node (P1 and a node (P9) at the reference potential; a first output (P4) for delivering a first voltage corresponding to the voltage at the terminals of the first capacitor (CNEG); a second output (P6) for delivering a second voltage corresponding to the voltage at the terminals of the second capacitor (CPOS); The power stage further comprises at least one comparator (40, 41) arranged to detect an inversion of the current in the inductor and the power stage is further arranged to close the fourth and fifth switches and to open the first, second and third switches upon detection of an inversion of the current in the inductor.
Abstract:
According to embodiments, dual path loop filter circuits are described which have, for example, a single charge pump. The current flow in the DPLF circuit is architected to source, during an injection time period, a first current to the loop filter, sink, also during the injection time period, a second current from the loop filter, wherein the first current has a magnitude of α*I and the second current has a magnitude of β*I, and sink, during a linearization time period, a third current from the loop filter, wherein the third current has a magnitude of (α−β)*I.
Abstract translation:根据实施例,描述了具有例如单个电荷泵的双路径环路滤波器电路。 在DPLF电路中的电流流动被设计成在注入时间段期间将源自环路滤波器的第一电流源自环路滤波器,也可以在注入时间段期间从环路滤波器引出第二电流,其中第一电流具有幅度 并且所述第二电流具有大于所述环路滤波器的第三电流,并且在线性化时间段期间从所述环路滤波器吸收第三电流,其中所述第三电流的幅度为(α&bgr)* I 。
Abstract:
A UE communication device is provided having a transmitter architecture that transmits SRS transmissions and PUSCH transmissions. A reference mode chosen from a LPM, an MPM and an HPM is selected based on a present power mode of the SRS transmission or based on a predicted power mode that the PUSCH transmission following the present SRS transmission will likely operate in. The transmitter architecture has an exemplary extended switching point structure allowing the RPD between the SRS transmission used for pre-quarter selection and the subsequent PUSCH transmission applying the pre-quarter to be minimized.
Abstract:
An apparatus (200) for use in a telecommunications system. The apparatus (200) comprising a memory (240) and a controller (210). The controller (210) is configured to receive a radio frequency bandwidth and identify a first candidate carrier frequency (710) from the received a radio frequency bandwidth. The controller is further configured to, for a first potential radio access technology determine a probability estimate (Prob) for the first candidate carrier frequency (710) being a carrier frequency of the first potential radio access technology, where in the probability estimate is based on a received power in a transmission band of the first potential radio access technology having the candidate carrier frequency (710) and on a received power in a guard band of the first potential radio access technology having the candidate carrier frequency and from this select a radio access technology based on the probability estimate (Prob) for the candidate carrier frequency (710).
Abstract:
The invention provides circuitry integrated into a silicon chip that measures aspects of an RF signal on a transmission line in order to provide data that is ultimately used by an antenna tuner circuit to substantially match the impedance of the antenna with that of the transmission line providing the RF frequency to be transmitted.
Abstract:
A built-in receiver self-test system provides on-chip testing with minimal change to the receiver footprint. The system digitally generates a two-tone test signal, and tests the nonlinearities of the receiver using the generated two-tone test signal. To that end, the self-test system comprises a stimulus generator, a downconverter, and a demodulator, all of which are disposed on a common receiver chip. The stimulus generator generates a test signal comprising first and second tones at respective first and second frequencies, where the first and second frequencies are spaced by an offset frequency, and where the first frequency comprises a non-integer multiple of the offset frequency. The downcoverter downconverts the test signal to generate an In-phase component and a Quadrature component. The demodulator measures an amplitude of the intermodulation tone by demodulating the In-phase and Quadrature components based on a reference frequency.
Abstract:
According to embodiments, dual path loop filter circuits are described which have, for example, a single charge pump. The current flow in the DPLF circuit is architected to source, during an injection time period, a first current to the loop filter, sink, also during the injection time period, a second current from the loop filter, wherein the first current has a magnitude of α*I and the second current has a magnitude of β*I, and sink, during a linearization time period, a third current from the loop filter, wherein the third current has a magnitude of (α−β)*I.
Abstract:
A current-mode regulator relies on indirect current measurement to facilitate slope compensation used to stabilize the operation of a buck converter. The current-mode regulator comprises an inductor, a switching network, and a controller. The inductor delivers an output current to a load. The switching network selectively connects the inductor input to an input voltage or a second voltage. The regulator controls the switching network. An inner loop control circuit of the regulator comprises the switching network, a current measuring circuit, a slope circuit, a comparator, and a switching controller. The current measuring circuit comprises a passive network connected to the inductor input and operative to indicate an inductor current as a measurement voltage. The slope circuit applies a time-varying voltage having a positive slope to the measurement voltage. The comparator compares a slope compensated measurement voltage to the control voltage. The switching regulator controls the switching network in response to the output of the comparator.