公开(公告)号：US09292362B2

公开(公告)日：2016-03-22

申请号：US13926089

申请日：2013-06-25

Applicant: Intel Corporation

Inventor： Lev Makovsky ,  Zeev Sperber ,  Efraim Rotem ,  Nir Rosenzweig ,  Stanislav Shwartsman ,  Raanan Sade ,  Igor Yanover ,  Gavri Berger ,  Tomer Weiner ,  Ron Gabor

IPC: G06F1/04 ,  G06F9/54 ,  G06F9/30 ,  G06F9/48 ,  G06F1/32

CPC classification number: G06F9/542 ,  G06F1/3206 ,  G06F9/30 ,  G06F9/4856 ,  Y02D10/24 ,  Y02D10/32

Abstract: In an embodiment, a processor includes at least a first core. The first core includes execution logic to execute operations, and a first event counter to determine a first event count associated with events of a first type that have occurred since a start of a first defined interval. The first core also includes a second event counter to determine a second event count associated with events of a second type that have occurred since the start of the first defined interval, and stall logic to stall execution of operations including at least first operations associated with events of the first type, until the first defined interval is expired responsive to the first event count exceeding a first combination threshold concurrently with the second event count exceeding a second combination threshold. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，处理器至少包括第一核。 第一核心包括执行操作的执行逻辑，以及第一事件计数器，用于确定与自第一定义间隔开始以来已经发生的第一类型的事件相关联的第一事件计数。 第一核心还包括第二事件计数器，用于确定与自第一定义间隔开始以来已经发生的第二类型的事件相关联的第二事件计数，以及停止逻辑以停止包括至少与事件相关联的第一操作的操作的执行 直到第一定义间隔响应于超过第一组合阈值的第一事件计数而超过第二事件计数超过第二组合阈值。 描述和要求保护其他实施例。

公开(公告)号：US08990512B2

公开(公告)日：2015-03-24

申请号：US13664682

申请日：2012-10-31

Applicant: Intel Corporation

Inventor： Stanislav Shwartsman ,  Raanan Sade ,  Larisa Novakovsky ,  Arijit Biswas

IPC: G06F12/00

CPC classification number: G06F12/121 ,  G06F11/1064 ,  G06F12/0811 ,  G06F12/0831 ,  G06F12/084 ,  G06F2212/1032 ,  G06T1/20

Abstract: A processor includes a core to execute instructions and a cache memory coupled to the core and having a plurality of entries. Each entry of the cache memory may include a data storage including a plurality of data storage portions, each data storage portion to store a corresponding data portion. Each entry may also include a metadata storage to store a plurality of portion modification indicators, each portion modification indicator corresponding to one of the data storage portions. Each portion modification indicator is to indicate whether the data portion stored in the corresponding data storage portion has been modified, independently of cache coherency state information of the entry. Other embodiments are described as claimed.

Abstract translation: 处理器包括执行指令的核心和耦合到核心并且具有多个条目的高速缓存存储器。 高速缓冲存储器的每个条目可以包括包括多个数据存储部分的数据存储部分，每个数据存储部分存储对应的数据部分。 每个条目还可以包括用于存储多个部分修改指示符的元数据存储器，每个部分修改指示符对应于数据存储部分之一。 每个部分修改指示符用于指示存储在相应的数据存储部分中的数据部分是否已被修改，而与条目的高速缓存一致性状态信息无关。 其他实施例被描述为所要求保护的。