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    Apparatus and method for power virus protection in a processor
    1.
    发明授权
    Apparatus and method for power virus protection in a processor 有权

    公开(公告)号：US12099597B2

    公开(公告)日：2024-09-24

    申请号：US18384996

    申请日：2023-10-30

    Applicant: Intel Corporation

    Inventor： Alexander Gendler ,  Sagi Meller ,  Gavri Berger ,  Igor Yanover

    IPC: G06F21/00 ,  G06F1/32 ,  G06F9/38 ,  G06F21/54 ,  G06F21/56

    CPC classification number: G06F21/54 ,  G06F1/32 ,  G06F9/3802 ,  G06F21/561 ,  G06F2221/034

    Abstract: An apparatus and method for intelligent power virus protection in a processor. For example, one embodiment of a processor comprises: first circuitry including an instruction fetch circuit to fetch instructions, each instruction comprising an instruction type and an associated width comprising a number of bits associated with source and/or destination operand values associated with the instruction; detection circuitry to detect one or more instructions of a particular type and/or width; evaluation circuitry to evaluate an impact of power virus protection (PVP) circuitry when executing the one or more instructions based on the detected instruction types and/or widths; and control circuitry, based on the evaluation, to configure the PVP circuitry in accordance with the evaluation performed by the evaluation circuitry.

    ADAPTIVE DYNAMIC DISPATCH OF MICRO-OPERATIONS
    4.
    发明公开
    ADAPTIVE DYNAMIC DISPATCH OF MICRO-OPERATIONS 审中-公开

    公开(公告)号：US20230205538A1

    公开(公告)日：2023-06-29

    申请号：US17561394

    申请日：2021-12-23

    Applicant: Intel Corporation

    Inventor： Or Beit Aharon ,  Zeev Sperber ,  Gavri Berger ,  Amit Gradstein ,  Nofar Hasson

    IPC: G06F9/38 ,  G06F9/30

    CPC classification number: G06F9/3836 ,  G06F9/30145 ,  G06F9/3001

    Abstract: Embodiments of apparatuses, methods, and systems for adaptive dynamic dispatch of micro-operations are disclosed. In an embodiment, an apparatus includes a plurality of redundant execution units, a dispatcher, control hardware, a first counter, and a second counter. The dispatcher is to dispatch micro-operations to one or more of the plurality of redundant execution units, the micro-operations having a plurality of micro-operation types. The first counter to generate a first count of dispatches, during a window, of micro-operations having a first type of the plurality of micro-operation types. The second counter to generate a second count of dispatches, during the window, of micro-operations having any type of the plurality of micro-operation types. The control hardware is to cause a switch between a first mode and a second mode based in part on the first count and the second count. In the first mode, the dispatcher is to dispatch micro-operations having the first type to only a subset of the plurality of redundant execution units. In the second mode, the dispatcher is to dispatch micro-operations having the first type to all of the plurality of redundant execution units.

    Accelerator systems and methods for matrix operations
    6.
    发明授权
    Accelerator systems and methods for matrix operations 有权

    公开(公告)号：US10942738B2

    公开(公告)日：2021-03-09

    申请号：US16368973

    申请日：2019-03-29

    Applicant: Intel Corporation

    Inventor： Zeev Sperber ,  Amit Gradstein ,  Simon Rubanovich ,  Igor Yanover ,  Gavri Berger ,  Eyal Hadas ,  Saeed Kharouf ,  Ron Schneider ,  Sagi Meller ,  Jose Yallouz

    IPC: G06F9/30 ,  G06F9/38

    Abstract: The present disclosure is directed to systems and methods for performing one or more operations on a two dimensional tile register using an accelerator that includes a tiled matrix multiplication unit (TMU). The processor circuitry includes reservation station (RS) circuitry to communicatively couple the processor circuitry to the TMU. The RS circuitry coordinates the operations performed by the TMU. TMU dispatch queue (TDQ) circuitry in the TMU maintains the operations received from the RS circuitry in the order that the operations are received from the RS circuitry. Since the duration of each operation is not known prior to execution by the TMU, the RS circuitry maintains shadow dispatch queue (RS-TDQ) circuitry that mirrors the operations in the TDQ circuitry. Communication between the RS circuitry 134 and the TMU provides the RS circuitry with notification of successfully executed operations and allows the RS circuitry to cancel operations where the operations are associated with branch mispredictions and/or non-retired speculatively executed instructions.

    Apparatuses, methods, and systems for instructions of a matrix operations accelerator
    8.
    发明授权
    Apparatuses, methods, and systems for instructions of a matrix operations accelerator 有权

    公开(公告)号：US12204605B2

    公开(公告)日：2025-01-21

    申请号：US18360793

    申请日：2023-07-27

    Applicant: Intel Corporation

    Inventor： Amit Gradstein ,  Simon Rubanovich ,  Sagi Meller ,  Saeed Kharouf ,  Gavri Berger ,  Zeev Sperber ,  Jose Yallouz ,  Ron Schneider

    IPC: G06F17/16 ,  G06F9/30 ,  G06F9/38 ,  G06F9/34

    Abstract: Systems, methods, and apparatuses relating to a matrix operations accelerator are described. In one embodiment, a processor includes a matrix operations accelerator circuit that includes a two-dimensional grid of fused multiply accumulate circuits that is switchable to a scheduling mode for execution of a decoded single instruction where the matrix operations accelerator circuit loads a first buffer of the two-dimensional grid of fused multiply accumulate circuits from a first plurality of registers that represents a first input two-dimensional matrix, checks if a second buffer of the two-dimensional grid of fused multiply accumulate circuits stores an immediately prior input two-dimension matrix that is the same as a second input two-dimensional matrix from a second plurality of registers that represents the first input two-dimensional matrix, and when the second buffer of the two-dimensional grid of fused multiply accumulate circuits stores the immediately prior input two-dimension matrix, from execution of a previous instruction, that is the same as the second input two-dimensional matrix: prevents reclamation of the second buffer between execution of the previous instruction and the decoded single instruction, performs an operation on the first input two-dimensional matrix from the first buffer and the immediately prior input two-dimension matrix from the second buffer to produce a resultant, and stores the resultant in resultant storage, and when the second buffer of the two-dimensional grid of fused multiply accumulate circuits does not store the immediately prior input two-dimension matrix, from execution of the previous instruction, that is the same as the second input two-dimensional matrix: loads the second input two-dimensional matrix into the second buffer of the two-dimensional grid of fused multiply accumulate circuits, performs the operation on the first input two-dimensional matrix from the first buffer and the second input two-dimension matrix from the second buffer to produce a resultant, and stores the resultant in the resultant storage.

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