公开(公告)号：US11410949B2

公开(公告)日：2022-08-09

申请号：US16940040

申请日：2020-07-27

Applicant: Micron Technology, Inc.

Inventor： Eric N. Lee ,  Akira Goda

IPC: H01L23/00 ,  H01L25/18 ,  H01L23/48 ,  H01L21/48 ,  H01L27/11519 ,  H01L27/11529 ,  H01L27/1157 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11524

Abstract: An apparatus is provided, comprising a substrate with a frontside and a backside opposite the frontside; control circuitry disposed over the frontside of the substrate; a memory array disposed over and electrically coupled to the control circuitry; a through-silicon via (TSV) disposed under the memory array, the TSV extending through the substrate from the control circuitry to the backside of the substrate; and a bond pad disposed on the backside of the substrate and electrically coupled to the control circuitry via the TSV.

公开(公告)号：US11335418B2

公开(公告)日：2022-05-17

申请号：US17135321

申请日：2020-12-28

Applicant: Micron Technology, Inc.

Inventor： Eric N. Lee ,  Lawrence Celso Miranda

IPC: G11C11/34 ,  G11C16/34 ,  G11C16/26 ,  G11C16/10 ,  G11C16/30

Abstract: Some embodiments include apparatus and methods using access lines, first memory cells coupled to an access line of the access lines, and a control unit including circuitry. The control unit is configured to apply a first voltage to the access line; check first threshold voltages of the first memory cells after applying the first voltage; obtain offset information based on a determination that at least one of the first threshold voltages is greater than a selected voltage; generate a second voltage, the second voltage being a function of the first voltage and the offset information; and apply the second voltage to one of the access lines during an operation of storing information in second memory cells.

公开(公告)号：US11043507B2

公开(公告)日：2021-06-22

申请号：US16554943

申请日：2019-08-29

Applicant: Micron Technology, Inc.

Inventor： Eric N. Lee

IPC: H01L27/11582 ,  H01L27/11548 ,  H01L27/11556 ,  G11C11/4097 ,  G11C11/419 ,  H01L29/66

Abstract: A semiconductor device structure comprises blocks having substantially uniform pitch laterally-extending throughout a first region, a second region laterally-neighboring the first memory region, and a third region laterally-neighboring the second region; memory strings longitudinally-extending through a first portion of the blocks located in the first region; pillar structures longitudinally-extending through a second portion of the blocks located in the second region; conductive contacts longitudinally-extending through a third portion of the blocks located in the third region; and conductive line structures electrically coupled to and laterally-extending between the memory strings and the conductive contacts. Each of the blocks comprises tiers, each tier comprising a conductive structure and an insulating structure longitudinally-neighboring the conductive structure. Semiconductor devices and electronic systems are also described.

公开(公告)号：US20210143169A1

公开(公告)日：2021-05-13

申请号：US17152186

申请日：2021-01-19

Applicant: Micron Technology, Inc.

Inventor： Eric N. Lee

IPC: H01L27/11575 ,  H01L23/528 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11548 ,  H01L27/11526 ,  H01L27/11573 ,  H01L21/764 ,  H01L27/11524 ,  H01L27/1157

Abstract: A semiconductor device structure comprises stacked tiers each comprising at least one conductive structure and at least one insulating structure longitudinally adjacent the at least one conductive structure, at least one staircase structure having steps comprising lateral ends of the stacked tiers, and at least one opening extending through the stacked tiers and continuously across an entire length of the at least one staircase structure. The at least one conductive structure of each of the stacked tiers extends continuously from at least one of the steps of the at least one staircase structure and around the at least one opening to form at least one continuous conductive path extending completely across each of the stacked tiers. Additional semiconductor device structures, methods of forming semiconductor device structures, and electronic systems are also described.

公开(公告)号：US20210110856A1

公开(公告)日：2021-04-15

申请号：US17247267

申请日：2020-12-07

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kaveh Shakeri ,  Ali Feiz Zarrin Ghalam ,  Qiang Tang ,  Eric N. Lee

IPC: G11C7/22 ,  G11C7/06 ,  G11C8/06 ,  G11C8/04 ,  G11C7/10 ,  G11C8/18

Abstract: A system might include a first writing device and a second writing device. The first writing device might write first data to an array of memory cells in response to a first clock cycle of a clock signal. The write of the first data exceeds one clock cycle of the clock signal. The second writing device is in parallel with the first writing device. The second writing device might write second data to the array of memory cells in response to a second clock cycle of the clock signal. The second clock cycle follows the first clock cycle and the write of the second data exceeds one clock cycle of the clock signal.

公开(公告)号：US10891993B2

公开(公告)日：2021-01-12

申请号：US16429209

申请日：2019-06-03

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kaveh Shakeri ,  Ali Feiz Zarrin Ghalam ,  Qiang Tang ,  Eric N. Lee

IPC: G11C7/10 ,  G11C7/22 ,  G11C7/06 ,  G11C8/06 ,  G11C8/04 ,  G11C8/18 ,  G11C16/04

Abstract: A wave pipeline includes a first stage, a plurality of second stages, and a third stage. The first stage receives a data signal representative of data and a clock signal, and may process the data at a first data rate equal to a clock rate of the clock signal. Each second stage may process respective data in response to a respective clock cycle received from the first stage at a second data rate equal to the first data rate times the number of second stages. The third stage may process data received from each second stage at the first data rate. The first stage divides the data signal and the clock signal between the plurality of second stages. The third stage merges the respective data and the respective clock cycles from each of the plurality of second stages to provide a merged data signal and a return clock signal.

公开(公告)号：US10650895B2

公开(公告)日：2020-05-12

申请号：US16446234

申请日：2019-06-19

Applicant: Micron Technology, Inc.

Inventor： Eric N. Lee

IPC: G11C16/08 ,  G11C16/04 ,  G11C5/02 ,  G11C8/08 ,  G11C8/12

Abstract: Memory device having a tile architecture are disclosed. The memory device may include a first plane having multiple pairs of tiles, wherein at least some of the pairs of tiles of the first plane include a distributed block select circuit and page buffer circuitry. Another memory device may include a memory array, and a CMOS under array region. At least some tile regions may include portions of a total amount of block select circuitry distributed throughout the CUA region, vertical string drivers located outside of the memory array, and page buffer circuitry coupled with the memory array. Another memory device may include a first tile pair including a first tile, a second tile, a first vertical string driver therebetween, a first page buffer region that is greater than 50% of area for the first tile pair, and a first portion of a distributed block select circuitry.

公开(公告)号：US10580791B1

公开(公告)日：2020-03-03

申请号：US16106752

申请日：2018-08-21

Applicant: Micron Technology, Inc.

Inventor： Eric N. Lee

IPC: H01L27/11582 ,  H01L27/11548 ,  G11C11/419 ,  G11C11/4097 ,  H01L27/11556

Abstract: A semiconductor device structure comprises blocks having substantially uniform pitch laterally-extending throughout a first region, a second region laterally-neighboring the first memory region, and a third region laterally-neighboring the second region; memory strings longitudinally-extending through a first portion of the blocks located in the first region; pillar structures longitudinally-extending through a second portion of the blocks located in the second region; conductive contacts longitudinally-extending through a third portion of the blocks located in the third region; and conductive line structures electrically coupled to and laterally-extending between the memory strings and the conductive contacts. Each of the blocks comprises tiers, each tier comprising a conductive structure and an insulating structure longitudinally-neighboring the conductive structure. Semiconductor devices and electronic systems are also described.

公开(公告)号：US20200066752A1

公开(公告)日：2020-02-27

申请号：US16554943

申请日：2019-08-29

Applicant: Micron Technology, Inc.

Inventor： Eric N. Lee

IPC: H01L27/11582 ,  H01L27/11548 ,  G11C11/419 ,  G11C11/4097 ,  H01L27/11556

Abstract: A semiconductor device structure comprises blocks having substantially uniform pitch laterally-extending throughout a first region, a second region laterally-neighboring the first memory region, and a third region laterally-neighboring the second region; memory strings longitudinally-extending through a first portion of the blocks located in the first region; pillar structures longitudinally-extending through a second portion of the blocks located in the second region; conductive contacts longitudinally-extending through a third portion of the blocks located in the third region; and conductive line structures electrically coupled to and laterally-extending between the memory strings and the conductive contacts. Each of the blocks comprises tiers, each tier comprising a conductive structure and an insulating structure longitudinally-neighboring the conductive structure. Semiconductor devices and electronic systems are also described.

公开(公告)号：US10453533B2

公开(公告)日：2019-10-22

申请号：US15816484

申请日：2017-11-17

Applicant: Micron Technology, Inc.

Inventor： Eric N. Lee

IPC: G11C16/08 ,  G11C16/04 ,  G11C8/08 ,  G11C8/12 ,  G11C5/02

Abstract: Memory device having a tile architecture are disclosed. The memory device may include a first plane having multiple pairs of tiles, wherein at least some of the pairs of tiles of the first plane include a distributed block select circuit and page buffer circuitry. Another memory device may include a memory array, and a CMOS under array region. At least some tile regions may include portions of a total amount of block select circuitry distributed throughout the CUA region, vertical string drivers located outside of the memory array, and page buffer circuitry coupled with the memory array. Another memory device may include a first tile pair including a first tile, a second tile, a first vertical string driver therebetween, a first page buffer region that is greater than 50% of area for the first tile pair, and a first portion of a distributed block select circuitry.