公开(公告)号：US20220075532A1

公开(公告)日：2022-03-10

申请号：US17391898

申请日：2021-08-02

Applicant: Micron Technology, Inc.

Inventor： Scott E. Schaefer

IPC: G06F3/06

Abstract: Methods, systems, and devices for selectable error control for memory device are described. An apparatus may include a memory array and a circuit configurable to perform a first error control operation and a second error control operation on data stored by the memory array. The circuit may include a first plurality of gates enabled during the first error control operation and configured to generate a first set of bits associated with a first matrix of the first error control operation. The circuit may also include a second plurality of gates enabled during the second error control operation and configured to generate a second set of bits associated with the second matrix of the second error control operation. The circuit may further include a third plurality of gates configured to generate a third set of bits that are common to both the first matrix and the second matrix.

公开(公告)号：US11216333B2

公开(公告)日：2022-01-04

申请号：US16579219

申请日：2019-09-23

Applicant: Micron Technology, Inc.

Inventor： Scott E. Schaefer ,  Aaron P. Boehm

IPC: G06F11/00 ,  G06F11/10 ,  G06F11/07 ,  G06F13/28

Abstract: Methods, systems, and devices are described herein for using codewords to detect or correct errors in data (e.g., data stored in a memory device). A host device may generate one or more codewords associated with data to be stored in the memory device. In some cases, the host device may generate one or more codewords for error detection and correction (e.g., corresponding to data transmitted by the host device to the memory device). In some cases, the host device may transmit the codewords and the associated data using an extended (e.g., adjustable) burst length such that the one or more codewords may be included in the burst along with the data. Additionally or alternatively, the host device may transmit one or more of the codewords over one or more channels different than the one or more channels used to transmit the data.

公开(公告)号：US20210397363A1

公开(公告)日：2021-12-23

申请号：US17345267

申请日：2021-06-11

Applicant: Micron Technology, Inc.

Inventor： Aaron P. Boehm ,  Todd J. Plum ,  Scott D. Van De Graaff ,  Scott E. Schaefer ,  Mark D. Ingram

IPC: G06F3/06 ,  G06F1/06

Abstract: Methods, systems, and devices for operational monitoring for memory devices are described. Some memory devices may degrade over time, and this degradation may include or refer to a reduction of an ability of the memory device to reliably store, read, process, or communicate information, among other degradation. In accordance with examples as disclosed herein, a memory device may include components configured for monitoring health or life expectancy or both of the memory device, such as components internal to the memory device that identify and store various indications of a duration of operating a memory device. An operational duration stored at the memory device may be used in various operations, such as calculations or comparisons, to evaluate health or life expectancy of the memory device, which may include or be supported by various signaling with a host device.

公开(公告)号：US11132147B2

公开(公告)日：2021-09-28

申请号：US16579095

申请日：2019-09-23

Applicant: Micron Technology, Inc.

Inventor： Scott E. Schaefer ,  Aaron P. Boehm

IPC: G06F3/06 ,  G06F9/30

Abstract: Methods, systems, and devices for performing memory command verification are described. A system may include a memory device and a memory controller, which may be external (e.g., a host device). The memory device may receive, from the memory controller, a command indicating a type of operation and an address. The memory device may decode the command and execute an operation (e.g., the operation corresponding to the decoded command) at an execution location on the memory device. The system (e.g., the memory device or the memory controller) may determine whether the executed operation and execution location match the type of operation and address indicated in the command, and the system may thereby determine an error associated with the decoding, the execution, or both of the command.

公开(公告)号：US20210157494A1

公开(公告)日：2021-05-27

申请号：US17090630

申请日：2020-11-05

Applicant: Micron Technology, Inc.

Inventor： Scott E. Schaefer ,  Aaron P. Boehm

IPC: G06F3/06

Abstract: Methods, systems, and devices for refresh counters in a memory system are described. In some examples, a memory device may include two or more counters configured to increment a respective count based on refresh operations performed on a memory array. A comparison may be made between two or more of the respective counts, which may include determining a difference between the respective counts or a difference in rate of incrementing. A memory device may transmit an indication to a host device based on determining a difference between counters, and the memory device, the host device, or both, may perform various operations or enter various operational modes based on the determined difference.

公开(公告)号：US10754801B2

公开(公告)日：2020-08-25

申请号：US16846146

申请日：2020-04-10

Applicant: Micron Technology, Inc.

Inventor： Scott E. Schaefer ,  Matthew A. Prather

IPC: G11C5/14 ,  G06F13/16 ,  G06F1/3206 ,  G06F5/06 ,  G06F1/3296 ,  G06F1/3234

Abstract: Memory devices and methods for operating the same are provided. A memory device can include at least one command contact and at least one data contact. The memory device can be configured to detect a condition in which the at least one command contact is connected to a controller and the at least one data contact is disconnected from the controller, and to enter, based at least in part on detecting the condition, a first operating mode with a lower nominal power rating than a second operating mode. Memory modules including one or more such memory devices can be provided, and memory systems including controllers and such memory modules can also be provided.

公开(公告)号：US20200258565A1

公开(公告)日：2020-08-13

申请号：US16786725

申请日：2020-02-10

Applicant: Micron Technology, Inc.

Inventor： Scott E. Schaefer ,  Aaron p. Boehm

IPC: G11C11/406

Abstract: Methods, systems, and devices for refresh rate control for a memory device are described. For example, a memory array of a memory device may be refreshed according to a first set of refresh parameters, such as a refresh rate. The memory device may detect an event at the memory device associated with a reduction in data integrity. In some cases, the event may be associated with a temperature of the memory device, a voltage level detected at the memory device, an error event at the memory device, or the like. As a result of detecting the event, the memory device may adapt one or more of the set of refresh parameters, such as increasing the refresh rate for the memory array. In some cases, the memory device may adapt the set of refresh parameters by increasing a quantity of rows of the memory array that are refreshed during a refresh operation, decreasing a periodicity between refresh operations, or both.

公开(公告)号：US20200081631A1

公开(公告)日：2020-03-12

申请号：US16546252

申请日：2019-08-20

Applicant: Micron Technology, Inc.

Inventor： Scott E. Schaefer ,  Aaron P. Boehm

IPC: G06F3/06

Abstract: Methods, systems, and devices for row hammer protection for a memory device are described. A memory device may identify a threshold of related row accesses (e.g., access commands or activates to a same row address or a row address space) for a memory array. In a first operation mode, the memory device may execute commands received from a host device on the memory array. The memory device may determine that a metric of the received row access commands satisfies the threshold of related row accesses. The memory device may switch the memory array from the first operation mode to a second operation mode based on satisfying the threshold. The second operation mode may restrict access to at least one row of the memory, while the first mode may be less restrictive. Additionally or alternatively, the memory device may notify the host device that the metric has satisfied the threshold.

公开(公告)号：US20250158639A1

公开(公告)日：2025-05-15

申请号：US19020935

申请日：2025-01-14

Applicant: Micron Technology, Inc.

Inventor： Aaron P. Boehm ,  Scott E. Schaefer

IPC: H03M13/15 ,  H03M13/00 ,  H03M13/11

Abstract: Methods, systems, and devices for error detection and classification at a host device are described. A host device may communicate a read command for a codeword stored at a memory device. In response to communicating the read command, the host device may receive the codeword and an error indication bit that indicates whether the memory device detected an error in the codeword. The host device may use the codeword to generate a set of syndrome bits. The host device may determine an error status of the codeword based on the error indication bit for the codeword and the set of syndrome bits for the codeword.

公开(公告)号：US20250047304A1

公开(公告)日：2025-02-06

申请号：US18804539

申请日：2024-08-14

Applicant: Micron Technology, Inc.

Inventor： Scott E. Schaefer

IPC: H03M13/11 ,  H03M13/00 ,  H03M13/43

Abstract: Methods, systems, and devices for syndrome check functionality to differentiate between error types are described. A host system, a memory system, or some combination of both may include syndrome check circuitry to provide enhanced error diagnostic capabilities for data communicated between the host system and the memory system. The syndrome check circuitry may receive a first signal from the memory system indicating whether the memory system detected and attempted to correct an error in the data and may receive a second signal from the host system indicating whether the host system detected an error in the received data. The syndrome check circuitry may compare the first signal and the second signal using a set of logic gates to differentiate between different combinations of errors detected at one or both of the memory system or the host system.