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    Chiplets 3D SoIC System Integration and Fabrication Methods
    111.
    发明申请
    Chiplets 3D SoIC System Integration and Fabrication Methods 有权

    公开(公告)号：US20210366854A1

    公开(公告)日：2021-11-25

    申请号：US17077618

    申请日：2020-10-22

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chen-Hua Yu ,  Kuo-Chung Yee

    IPC: H01L23/00 ,  H01L23/48

    Abstract: A method includes forming integrated circuits on a front side of a first chip, performing a backside grinding on the first chip to reveal a plurality of through-vias in the first chip, and forming a first bridge structure on a backside of the first chip using a damascene process. The bridge structure has a first bond pad, a second bond pad, and a conductive trace electrically connecting the first bond pad to the second bond pad. The method further includes bonding a second chip and a third chip to the first chip through face-to-back bonding. A third bond pad of the second chip is bonded to the first bond pad of the first chip. A fourth bond pad of the third chip is bonded to the second bond pad of the first chip.

    Chip package
    112.
    发明授权
    Chip package 有权

    公开(公告)号：US11177434B2

    公开(公告)日：2021-11-16

    申请号：US16991039

    申请日：2020-08-12

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chen-Hua Yu ,  Kuo-Chung Yee

    IPC: H01L29/40 ,  H01L21/44 ,  H01L45/00 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18

    Abstract: An integrated fan-out package including an integrated circuit, a plurality of memory devices, an insulating encapsulation, and a redistribution circuit structure is provided. The memory devices are electrically connected to the integrated circuit. The integrated circuit and the memory devices are stacked, and the memory devices are embedded in the insulating encapsulation. The redistribution circuit structure is disposed on the insulating encapsulation, and the redistribution circuit structure is electrically connected to the integrated circuit and the memory devices. Furthermore, methods for fabricating the integrated fan-out package are also provided.

    Wafer Level Package Structure and Method of Forming Same
    113.
    发明申请
    Wafer Level Package Structure and Method of Forming Same 有权

    公开(公告)号：US20210351076A1

    公开(公告)日：2021-11-11

    申请号：US17379775

    申请日：2021-07-19

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chen-Hua Yu ,  Kuo-Chung Yee ,  Mirng-Ji Lii ,  Chien-Hsun Lee ,  Jiun Yi Wu

    IPC: H01L21/768 ,  H01L25/00 ,  H01L21/56 ,  H01L23/00 ,  H01L25/10

    Abstract: An embodiment is a package including a first package component. The first package component including a first die attached to a first side of a first interconnect structure, a molding material surrounding the first die, and a second interconnect structure over the molding material and the first die, a first side of the second interconnect structure coupled to the first die with first electrical connectors. The first package component further includes a plurality of through molding vias (TMVs) extending through the molding material, the plurality of TMVs coupling the first interconnect structure to the second interconnect structure, and a second die attached to a second side of the second interconnect structure with second electrical connectors, the second side of the second interconnect structure being opposite the first side of the second interconnect structure.

    Semiconductor device including through die via and manufacturing method thereof
    116.
    发明授权
    Semiconductor device including through die via and manufacturing method thereof 有权

    公开(公告)号：US11075145B2

    公开(公告)日：2021-07-27

    申请号：US16413607

    申请日：2019-05-16

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chen-Hua Yu ,  Kuo-Chung Yee

    IPC: H01L23/48 ,  H01L23/31 ,  H01L23/00 ,  H01L21/768

    Abstract: A semiconductor device and a manufacturing method thereof are provided. A semiconductor device includes a first semiconductor die, a second semiconductor die, a bonding layer, and a through die via. The first semiconductor die includes a first semiconductor substrate and a first conductive pad exposed at an active surface of the first semiconductor die. The second semiconductor die includes a second semiconductor substrate and a second conductive pad exposed at an active surface of the second semiconductor die. The first semiconductor die is stacked over the second semiconductor die. The bonding layer is disposed between the first and the second semiconductor die. The through die via electrically connects the first semiconductor die and the second semiconductor die. The through die via is embedded in the first semiconductor substrate, penetrates through the first conductive pad and the bonding layer, and reaches the second conductive pad.

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