公开(公告)号：US20200013636A1

公开(公告)日：2020-01-09

申请号：US16575698

申请日：2019-09-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Hao Tseng ,  Ying-Hao Kuo ,  Kuo-Chung Yee

IPC: H01L21/48 ,  H01L23/00 ,  H01L23/36 ,  H01L23/373 ,  H01L23/31 ,  H01L21/56 ,  H01L25/065 ,  H01L25/00

Abstract: A method of forming a semiconductor package includes providing a substrate, wherein the substrate has at least one chip attached on an upper surface of the substrate. An insulating barrier layer is deposited above the substrate, wherein the at least one chip is at least partially embedded within the insulating barrier layer. A thermally conductive layer is formed over the insulating barrier layer to at least partially encapsulate the at least one chip.

公开(公告)号：US20190025514A1

公开(公告)日：2019-01-24

申请号：US16141621

申请日：2018-09-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Hao Tseng ,  Ying-Hao Kuo ,  Kai-Fang Cheng ,  Hai-Ching Chen ,  Tien-I Bao

IPC: G02B6/132 ,  H01L21/56 ,  G02B6/136 ,  H01L29/06 ,  H01L23/31 ,  G02B6/122 ,  H01L21/48 ,  G02B6/138 ,  G02B6/12

Abstract: An apparatus comprises a substrate having a plateau region and a trench region, a metal layer over the plateau region, a semiconductor component over the trench region, wherein a gap is between the plateau region and the semiconductor component, an adhesion promoter layer over the plateau region, the semiconductor component and the gap, a dielectric layer over the adhesion promoter layer and a bonding interface formed between the adhesion promoter layer and the dielectric layer, wherein the bonding interface comprises a chemical structure comprising a first dielectric material of the adhesion promoter layer and a second dielectric material of the dielectric layer.

公开(公告)号：US20170140945A1

公开(公告)日：2017-05-18

申请号：US15418949

申请日：2017-01-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Hao Tseng ,  Ying-Hao Kuo ,  Kuo-Chung Yee

IPC: H01L21/48 ,  H01L23/31 ,  H01L25/00 ,  H01L21/56 ,  H01L23/00 ,  H01L25/065 ,  H01L23/373

Abstract: A method of forming a semiconductor package includes providing a substrate, wherein the substrate has at least one chip attached on an upper surface of the substrate. An insulating barrier layer is deposited above the substrate, wherein the at least one chip is at least partially embedded within the insulating barrier layer. A thermally conductive layer is formed over the insulating barrier layer to at least partially encapsulate the at least one chip.

公开(公告)号：US11574886B2

公开(公告)日：2023-02-07

申请号：US17104588

申请日：2020-11-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Hao Tseng ,  Ying-Hao Kuo ,  Kuo-Chung Yee

IPC: H01L23/31 ,  H01L23/42 ,  H01L23/00 ,  H01L23/373 ,  H01L21/56 ,  H01L23/433

Abstract: The present disclosure, in some embodiments, relates to a semiconductor package. The semiconductor package includes a first chip and a second chip attached to a substrate. A thermal conductivity layer is attached to the first chip. A molding compound laterally surrounds the first chip, the second chip, and the thermal conductivity layer. The second chip extends from the substrate to an imaginary horizontally extending line that extends along a horizontally extending surface of the thermal conductivity layer facing away from the substrate. The imaginary horizontally extending line is parallel to the horizontally extending surface.

公开(公告)号：US20210202270A1

公开(公告)日：2021-07-01

申请号：US17205146

申请日：2021-03-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Hao Tseng ,  Ying-Hao Kuo ,  Kuo-Chung Yee

IPC: H01L21/48 ,  H01L23/00 ,  H01L23/36 ,  H01L23/373 ,  H01L23/31 ,  H01L21/56 ,  H01L25/065 ,  H01L25/00

Abstract: A semiconductor package includes a wafer and at least one chip attached on first portions of an upper surface of the wafer. Further, the semiconductor package includes an insulating barrier layer, a thermally conductive layer, and a heat sink. The insulating barrier layer is arranged over the at least one chip attached on first portions of an upper surface of the wafer. The thermally conductive layer is arranged over the insulating barrier layer and at least partially encapsulates the at least one chip. The heat sink is arranged over the thermally conductive layer.

公开(公告)号：US20200020658A1

公开(公告)日：2020-01-16

申请号：US16578358

申请日：2019-09-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Hao Tseng ,  Ying-Hao Kuo ,  Kuo-Chung Yee

IPC: H01L23/00 ,  H01L23/42 ,  H01L23/373

Abstract: The present disclosure, in some embodiments, relates to a method of forming a semiconductor package. The method may be performed by attaching a first thermal conductivity layer to an upper surface of a first chip, and attaching a second thermal conductivity layer to an upper surface of a second chip. A first support substrate is attached to lower surfaces of the first chip and the second chip. A molding compound is formed over the first support substrate and laterally surrounds the first chip and the second chip. The first support substrate is replaced with a package substrate after forming the molding compound over the first support substrate.

公开(公告)号：US10510707B2

公开(公告)日：2019-12-17

申请号：US15966426

申请日：2018-04-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Hao Tseng ,  Ying-Hao Kuo ,  Kuo-Chung Yee

IPC: H01L23/42 ,  H01L23/00 ,  H01L23/373

Abstract: A method of forming a semiconductor package includes attaching a thermal conductivity layer to a chip. The chip has a first surface and a second surface. The thermal conductivity layer is attached to the first surface of the chip. The thermal conductivity layer provides a path through which heat generated from the chip is dissipated to the ambient. A substrate is attached to the second surface of the chip after attaching the thermal conductivity layer to the chip. A molding compound is formed to encapsulate the chip and the thermal conductivity layer.

公开(公告)号：US10784227B2

公开(公告)日：2020-09-22

申请号：US16578358

申请日：2019-09-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Hao Tseng ,  Ying-Hao Kuo ,  Kuo-Chung Yee

IPC: H01L21/56 ,  H01L23/42 ,  H01L23/31 ,  H01L23/00 ,  H01L23/373 ,  H01L23/433

Abstract: The present disclosure, in some embodiments, relates to a method of forming a semiconductor package. The method may be performed by attaching a first thermal conductivity layer to an upper surface of a first chip, and attaching a second thermal conductivity layer to an upper surface of a second chip. A first support substrate is attached to lower surfaces of the first chip and the second chip. A molding compound is formed over the first support substrate and laterally surrounds the first chip and the second chip. The first support substrate is replaced with a package substrate after forming the molding compound over the first support substrate.

公开(公告)号：US10541154B2

公开(公告)日：2020-01-21

申请号：US15418949

申请日：2017-01-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Hao Tseng ,  Ying-Hao Kuo ,  Kuo-Chung Yee

IPC: H01L21/48 ,  H01L23/00 ,  H01L23/36 ,  H01L23/373 ,  H01L23/31 ,  H01L21/56 ,  H01L25/065 ,  H01L25/00

Abstract: A method of forming a semiconductor package includes providing a substrate, wherein the substrate has at least one chip attached on an upper surface of the substrate. An insulating barrier layer is deposited above the substrate, wherein the at least one chip is at least partially embedded within the insulating barrier layer. A thermally conductive layer is formed over the insulating barrier layer to at least partially encapsulate the at least one chip.

公开(公告)号：US20190237379A1

公开(公告)日：2019-08-01

申请号：US16382542

申请日：2019-04-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wan-Yu Lee ,  Chun-Hao Tseng ,  Jui Hsieh Lai ,  Tien-Yu Huang ,  Ying-Hao Kuo ,  Kuo-Chung Yee

IPC: H01L23/31 ,  H01L33/48 ,  H01L21/56 ,  H01L21/311 ,  H01L21/48 ,  H01L21/50 ,  H01L31/09 ,  H01L31/0232 ,  H01L31/0203 ,  H01L27/146 ,  H01L25/00 ,  H01L25/16 ,  H01L23/00 ,  H01L23/538 ,  H01L23/485 ,  H01L23/48 ,  H01L23/29 ,  H01L23/28 ,  H01L21/768 ,  H01L21/683 ,  H01L33/52

Abstract: In some embodiments, the present disclosure relates to a package for holding a plurality of integrated circuits. The package includes a first conductive pad disposed over a first substrate and a second conductive pad disposed over a second substrate. The second conductive pad is a multi-layer structure having an uppermost metal layer including titanium or nickel. A molding structure surrounds the first substrate and the second substrate. A conductive structure is over the first substrate and the second substrate. The conductive structure is conductively coupled to the second conductive pad.