公开(公告)号：US11444195B2

公开(公告)日：2022-09-13

申请号：US17118524

申请日：2020-12-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Yu Yang

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/08 ,  H01L21/033 ,  H01L21/324 ,  H01L21/225 ,  H01L21/306 ,  H01L29/10

Abstract: A method of forming a semiconductor structure is disclosed. First, a substrate is provided, including an upper surface. A gate structure is disposed on the upper surface. A spacer is disposed on a sidewall of the gate structure. A first region is located in the substrate. A second region is located in the substrate. The first region and the second region are dry etched to form a first trench and a second trench, respectively. The second region is masked. The first region is then wet etched through the first trench to form a widened first trench. A stress-inducing layer is then formed in the widened first trench and in the second trench.

公开(公告)号：US20220271032A1

公开(公告)日：2022-08-25

申请号：US17735114

申请日：2022-05-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Yu Yang ,  Yu-Wen Hung

IPC: H01L27/092 ,  H01L29/08 ,  H01L29/06 ,  H01L29/423 ,  H01L29/10

Abstract: A manufacturing method of a semiconductor device is provided in an embodiment of the present invention. The manufacturing method includes the following steps. A transistor is formed on a substrate. The transistor includes a plurality of semiconductor sheets and two source/drain structures. The semiconductor sheets are stacked in a vertical direction and separated from one another. Each of the semiconductor sheets includes two first doped layers and a second doped layer disposed between the two first doped layers in the vertical direction. A conductivity type of the second doped layer is complementary to a conductivity type of each of the two first doped layers. The two source/drain structures are disposed at two opposite sides of each of the semiconductor sheets in a horizontal direction respectively, and the two source/drain structures are connected with the semiconductor sheets.

公开(公告)号：US20220271001A1

公开(公告)日：2022-08-25

申请号：US17200931

申请日：2021-03-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Yu Yang

IPC: H01L23/00

Abstract: A semiconductor structure includes a first substrate including a first contact structure located on a first pad, and a second substrate including a second contact structure on a second pad. The first contact structure includes a first metal base layer covered by a first nano-twinned metal coating layer. The second contact structure includes a second nano-twinned metal coating layer on the second pad. The first contact structure is connected to the second contact structure, thereby forming a bonding interface between the first nano-twinned metal coating layer and the second nano-twinned metal coating layer.

公开(公告)号：US20220223706A1

公开(公告)日：2022-07-14

申请号：US17163589

申请日：2021-02-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Yu Yang

IPC: H01L29/423 ,  H01L27/092 ,  H01L29/786

Abstract: A semiconductor device includes a substrate and a first transistor disposed on the substrate. The first transistor includes a first semiconductor channel structure and two first source/drain structures. The first semiconductor channel structure includes first horizontal portions and a first vertical portion. The first horizontal portions are stacked in a vertical direction and separated from one another. Each of the first horizontal portions is elongated in a horizontal direction. The first vertical portion is elongated in the vertical direction and connected with the first horizontal portions. A material composition of the first vertical portion is identical to a material composition of each of the first horizontal portions. The two first source/drain structures are disposed at two opposite sides of each of the first horizontal portions in the horizontal direction respectively. The two first source/drain structures are connected with the first horizontal portions.

公开(公告)号：US11355494B1

公开(公告)日：2022-06-07

申请号：US17163586

申请日：2021-02-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Yu Yang ,  Yu-Wen Hung

IPC: H01L27/092 ,  H01L29/10 ,  H01L29/08 ,  H01L29/06 ,  H01L29/423

Abstract: A semiconductor device includes a substrate and a first transistor disposed on the substrate. The first transistor includes first semiconductor sheets and two first source/drain structures. The first semiconductor sheets are stacked in a vertical direction and separated from one another. Each of the first semiconductor sheets includes two first doped layers and a second doped layer disposed between the two first doped layers in the vertical direction. A conductivity type of the second doped layer is complementary to a conductivity type of each of the first doped layers. The two first source/drain structures are disposed at two opposite sides of each of the first semiconductor sheets in a horizontal direction respectively, and the two first source/drain structures are connected with the first semiconductor sheets.

公开(公告)号：US20220173217A1

公开(公告)日：2022-06-02

申请号：US17148539

申请日：2021-01-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Yu Yang

IPC: H01L29/417 ,  H01L29/06 ,  H01L29/66 ,  H01L29/778 ,  H01L29/40

Abstract: A semiconductor device includes a substrate, a semiconductor channel layer, a semiconductor barrier layer, a gate electrode, a first electrode, and a dielectric layer. The semiconductor channel layer is disposed on the substrate, and the semiconductor barrier layer is disposed on the semiconductor channel layer. The gate electrode is disposed on the semiconductor barrier layer. The first electrode is disposed at one side of the gate electrode. The first electrode includes a body portion and a vertical extension portion. The body portion is electrically connected to the semiconductor barrier layer, and the bottom surface of the vertical extension portion is lower than the top surface of the semiconductor channel layer. The dielectric layer is disposed between the vertical extension portion and the semiconductor channel layer.

公开(公告)号：US20210280706A1

公开(公告)日：2021-09-09

申请号：US17315380

申请日：2021-05-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Yu Yang

IPC: H01L29/778 ,  H01L21/762 ,  H01L29/20 ,  H01L29/66

Abstract: A method of fabricating high electron mobility transistor, including the steps of providing a substrate with active areas, forming a buffer layer, a channel layer and a barrier layer sequentially on the substrate and gate, source and drain on the barrier layer, forming a trench surrounding the channel layer and the barrier layer, and forming a trench isolation structure in the trench, wherein the trench isolation structure applies stress on the channel layer and the barrier layer and modify two-dimension electron gas (2DEG) or two-dimension hole gas (2DHG) of the high electron mobility transistor.

公开(公告)号：US20210217885A1

公开(公告)日：2021-07-15

申请号：US17197075

申请日：2021-03-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Yu Yang

IPC: H01L29/778 ,  H01L21/02 ,  H01L29/205 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66

Abstract: A method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a buffer layer on a substrate; forming a first barrier layer on the buffer layer; forming a patterned mask on the first barrier layer; forming a second barrier layer adjacent to two sides of the patterned mask; removing the patterned mask to form a recess; forming a gate electrode in the recess; and forming a source electrode and a drain electrode adjacent to two sides of the gate electrode.

公开(公告)号：US11038066B2

公开(公告)日：2021-06-15

申请号：US16819148

申请日：2020-03-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Yu Yang

IPC: H01L29/76 ,  H01L29/786 ,  H01L27/092 ,  H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L27/12 ,  H01L27/088 ,  H01L29/775 ,  H01L29/66

Abstract: A nanowire transistor structure includes a substrate. A first nanowire is suspended on the substrate. A first gate line crosses and surrounds the first nanowire. The first gate line includes a first end and a second end. A second gate line crosses and surrounds the first nanowire. The second gate line includes a third end and a fourth end. An interlayer dielectric encapsulates the first end, the second end, the third end and the fourth end. A first distance between the first end and the first nanowire is smaller than a third distance between the third end and the first nanowire.

公开(公告)号：US11011486B1

公开(公告)日：2021-05-18

申请号：US16675200

申请日：2019-11-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Yu Yang

IPC: H01L23/52 ,  H01L23/00 ,  H01L25/065

Abstract: A semiconductor structure is disclosed, including a substrate, an insulating layer on the substrate, a barrier layer on the insulating layer, a bonding dielectric layer on the barrier layer, and a bonding pad extending through the insulating layer, the barrier layer and the bonding dielectric layer. A top surface of the bonding pad exposed from the bonding dielectric layer for bonding to another bonding pad on another substrate. A liner on a bottom surface of the bonding pad directly contacts the substrate.