公开(公告)号：US20230314506A1

公开(公告)日：2023-10-05

申请号：US18186624

申请日：2023-03-20

Applicant: STMicroelectronics International N.V. ,  STMicroelectronics Application GmbH

Inventor： Roberto Colombo ,  Vivek Mohan Sharma

IPC: G01R31/317 ,  G01R31/3185

CPC classification number: G01R31/31721 ,  G01R31/31724 ,  G01R31/318566

Abstract: In an embodiment a processing system includes a reset circuit configured to receive a reset-request signal and one or more further reset-request signals, wherein the one or more further reset-request signals are provided by a processing core, one or more further circuits and/or a terminal of the processing system and to generate a combined reset-request signal by combining the reset-request signal and the one or more further reset-request signals, and a hardware test circuit including for each of the one or more further reset-request signals, a respective first combinational circuit configured to selectively assert the respective further reset-request signal, a second combinational logic circuit configured to selectively mask the combined reset-request signal, and a control circuit configured to repeat operations during a diagnostic phase.

公开(公告)号：US11734221B2

公开(公告)日：2023-08-22

申请号：US17199418

申请日：2021-03-11

Applicant: STMicroelectronics Application GMBH ,  STMICROELECTRONICS DESIGN AND APPLICATION S.R.O.

Inventor： Rolf Nandlinger ,  Radek Olexa

IPC: G06F13/42 ,  G06F9/30 ,  G06F13/16 ,  G06F13/40

CPC classification number: G06F13/4291 ,  G06F9/30134 ,  G06F13/1673 ,  G06F13/4031

Abstract: An embodiment processing system comprises a queued SPI circuit, which comprises a hardware SPI communication interface, an arbiter and a plurality of interface circuits. Each interface circuit comprises a transmission FIFO memory, a reception FIFO memory and an interface control circuit. The interface control circuit is configured to receive first data packets and store them to the transmission FIFO memory. The interface control circuit sequentially reads the first data packets from the transmission FIFO memory, extracts at least one transmission data word, and provides the extracted word to the arbiter. The interface control circuit receives from the arbiter a reception data word and stores second data packets comprising the received reception data word to the reception FIFO memory. The interface control circuit sequentially reads the second data packets from the reception FIFO memory and transmits them to the digital processing circuit.

公开(公告)号：US11677648B2

公开(公告)日：2023-06-13

申请号：US17182914

申请日：2021-02-23

Applicant: STMicroelectronics Application GMBH

Inventor： Fred Rennig

IPC: H04L43/08 ,  H04L12/40

CPC classification number: H04L43/08 ,  H04L12/40 ,  H04L2012/40215

Abstract: In accordance with an embodiment, a method includes determining whether a frame received from a communication bus is encoded according to a particular communication protocol and is addressed to a particular electronic device; increasing a frame count value when the frame is encoded according to the particular communication protocol and is addressed to the particular electronic device based on the determination, wherein increasing the frame count value comprises increasing a count of a modular arithmetic counter circuit having a first bit depth, and the frame count value is constrained to a modulus value of the modular arithmetic counter circuit; setting a frame count status bit based on comparing the frame count value to threshold values, and transmitting a frame comprising the frame counter status bit over the communication bus, and resetting the frame count value at an end of a monitoring time interval.

公开(公告)号：US11675721B2

公开(公告)日：2023-06-13

申请号：US17806587

申请日：2022-06-13

Applicant: STMicroelectronics Design & Application S.R.O. ,  STMicroelectronics Application GMBH

Inventor： Fred Rennig ,  Ludek Beran

IPC: G06F13/362 ,  G06F13/40 ,  G06F11/07 ,  G05B19/042 ,  G06F9/54 ,  H04L12/403 ,  H03M13/09

CPC classification number: G06F13/362 ,  G05B19/042 ,  G06F9/542 ,  G06F11/0739 ,  G06F11/0757 ,  G06F11/0772 ,  G06F13/4068 ,  H04L12/403 ,  G05B2219/1215 ,  G05B2219/2231 ,  G05B2219/31179 ,  H03M13/09

Abstract: A device includes a master device, a set of slave devices and a bus. The master device is configured to transmit first messages carrying a set of operation data message portions indicative of operations for implementation by slave devices of the set of slave devices, and second messages addressed to slave devices in the set of slave devices. The second messages convey identifiers identifying respective ones of the slave devices to which the second messages are addressed requesting respective reactions towards the master device within respective expected reaction intervals. The slave devices are configured to receive the first messages transmitted from the master device, read respective operation data message portions in the set of operation data message portions, implement respective operations as a function of the respective operation data message portions read, and receive the second messages transmitted from the master device.

公开(公告)号：US20230013396A1

公开(公告)日：2023-01-19

申请号：US17933680

申请日：2022-09-20

Applicant: STMicroelectronics Application GMBH

Inventor： Rolf Nandlinger

IPC: G06F1/14

Abstract: A processing system includes a digital processing unit programmable as a function of a firmware stored to a non-volatile memory and a resource connected to the digital processing unit via a communication system. The processing system also includes a time reference circuit including a first digital counter circuit to generate, in response to a clock signal, a system time signal including a plurality of bits indicative of a time tick-count, and a time base distribution circuit to generate a time base signal by selecting a subset of the bits of the system time signal, wherein the time base signal is provided to the resource. The resource detects a given event, stores the time base signal to a register in response to the event, and signals the event to the digital processing unit. The digital processing unit reads, via the communication system, the time base signal from the register.

公开(公告)号：US11474752B2

公开(公告)日：2022-10-18

申请号：US16932426

申请日：2020-07-17

Applicant: STMicroelectronics Application GmbH

Inventor： Roberto Colombo

IPC: G06F3/06 ,  G06F13/38 ,  G05B19/05 ,  G06F12/02 ,  G06F21/76

Abstract: A processing system comprises a processing unit, a hardware block configured to change operation as a function of life cycle data, and a one-time programmable memory storing original life cycle data. A hardware configuration module is configured to read the original life cycle data from the one-time programmable memory, to store the original life cycle data in a register, to receive a write request from the processing unit, and to selectively execute the write request to overwrite the original life cycle data with new life cycle data in the register.

公开(公告)号：US20220312566A1

公开(公告)日：2022-09-29

申请号：US17654532

申请日：2022-03-11

Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics S. r. l. ,  STMicroelectronics Application GMBH

Inventor： Manuel Gaertner ,  Philippe Sirito-Olivier ,  Giovanni Luca Torrisi ,  Thomas Urbitsch ,  Christophe Roussel ,  Fritz Burkhardt

IPC: H05B45/46 ,  H05B45/325 ,  H05B45/50 ,  H05B45/14

Abstract: A system includes lighting devices coupled to output supply pins, a microcontroller circuit, and a driver circuit, which receives data therefrom, and switches coupled in series to the lighting devices. The driver circuit includes output supply pins and selectively propagates a supply voltage to the output supply pins to provide respective pulse-width modulated supply signals at the output supply pins. The driver circuit computes duty-cycle values of the pulse-width modulated supply signals as a function of the data received from the microcontroller circuit. The lighting devices include at least one subset coupled to the same output supply pin. The microcontroller individually controls the switches via respective control signals to individually adjust a brightness of the lighting devices in the at least one subset of lighting devices.

公开(公告)号：US20220286319A1

公开(公告)日：2022-09-08

申请号：US17677113

申请日：2022-02-22

Applicant: STMicroelectronics Design and Application S.R.O. ,  STMicroelectronics Application GMBH

Inventor： Fred Rennig ,  Vaclav Dvorak

IPC: H04L12/403 ,  G06F9/30

Abstract: A circuit includes a first and a second memory, a processor and a timer. The processor generates a sequence of bits encoding a CAN frame and processes the sequence of bits to detect a sequence of PWM periods. The processor stores values of a first parameter of the PWM periods into the first memory, and values of a second parameter of the PWM periods into the second memory. The timer comprises a first register which reads from the first memory a value of the first parameter of a current PWM period. The timer comprises a counter which increases a count number and resets the count number as a function of the value of the first register.

公开(公告)号：US11366778B2

公开(公告)日：2022-06-21

申请号：US16874055

申请日：2020-05-14

Applicant: STMICROELECTRONICS DESIGN AND APPLICATION S.R.O. ,  STMICROELECTRONICS APPLICATION GMBH

Inventor： Fred Rennig ,  Ludek Beran

IPC: G06F13/362 ,  G06F13/40 ,  G06F11/07 ,  H04L12/403 ,  G05B19/042 ,  H03M13/09

Abstract: A device includes a master device, a set of slave devices and a bus. The master device is configured to transmit first messages carrying a set of operation data message portions indicative of operations for implementation by slave devices of the set of slave devices, and second messages addressed to slave devices in the set of slave devices. The second messages convey identifiers identifying respective ones of the slave devices to which the second messages are addressed requesting respective reactions towards the master device within respective expected reaction intervals. The slave devices are configured to receive the first messages transmitted from the master device, read respective operation data message portions in the set of operation data message portions, implement respective operations as a function of the respective operation data message portions read, and receive the second messages transmitted from the master device.

公开(公告)号：US11360143B2

公开(公告)日：2022-06-14

申请号：US17083876

申请日：2020-10-29

Applicant: STMicroelectronics International N.V. ,  STMicroelectronics Application GmbH ,  STMicroelectronics S.r.l.

Inventor： Avneep Kumar Goyal ,  Deepak Baranwal ,  Thomas Szurmant ,  Nicolas Bernard Grossier

IPC: G01R31/317 ,  G01R31/3185 ,  G01R31/3193 ,  G06F11/34 ,  G01R31/319 ,  G06F11/36

Abstract: A testing tool includes a clock generation circuit generating a test clock and outputting the test clock via a test clock output pad, data processing circuitry clocked by the test clock, and data output circuitry receiving data output from the data processing circuitry and outputting the data via an input/output (IO) pad, the data output circuitry being clocked by the test clock. The testing tool also includes a programmable delay circuit generating a delayed version of the test clock, and data input circuitry receiving data input via the IO pad, the data input circuitry clocked by the delayed version of the test clock. The delayed version of the test clock is delayed to compensate for delay between transmission of a pulse of the test clock via the test clock output pad to an external computer and receipt of the data input from the external computer via the IO pad.