公开(公告)号：US11170682B2

公开(公告)日：2021-11-09

申请号：US16651816

申请日：2019-03-25

Applicant: BOE Technology Group Co., Ltd.

Inventor： Guangliang Shang ,  Libin Liu ,  Can Zheng ,  Yipeng Chen ,  Xinshe Yin ,  Shiming Shi

IPC: G09G3/20 ,  G11C19/28

Abstract: Provided are a shift register and a driving method thereof, a gate driving circuit, and a display device. The shift register includes: an input circuit, configured to be coupled to an input signal end and a second clock signal end, respectively; a first transistor, where the first electrode of the first transistor is coupled to the output end of the input circuit, and the first transistor is a double-gate type transistor; the first gate of the first transistor is configured to be coupled to a first reference signal end, and the second gate of the first transistor is configured to be coupled to a first threshold control signal end; and an output circuit, configured to be coupled to a first clock signal end and a signal output end, respectively, where the control end of the output circuit is coupled to the second electrode of the first transistor.

公开(公告)号：US20210335314A1

公开(公告)日：2021-10-28

申请号：US16332902

申请日：2018-09-26

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Lijun Yuan ,  Seungwoo Han ,  Guangliang Shang

IPC: G09G3/36

Abstract: The present disclosure relates to a pixel circuit. The pixel circuit may include a switch sub-circuit (10), a storage sub-circuit (20), and a driving sub-circuit (30). The storage sub-circuit (20) may include a first storage transistor (Tf1) and a second storage transistor (Tf2). Both the first storage transistor (Tf1) and the second storage transistor (Tf2) may be floating gate transistors. The storage sub-circuit (20) and the driving sub-circuit (30) may be configured to transmit a data signal from one of a plurality of data lines to a pixel electrode under control of the switch sub-circuit (10).

公开(公告)号：US20210335210A1

公开(公告)日：2021-10-28

申请号：US16485994

申请日：2018-09-06

Applicant: BOE Technology Group Co., Ltd.

Inventor： Mingfu Han ,  Guangliang Shang ,  Xing Yao ,  Haoliang Zheng

IPC: G09G3/32

Abstract: The present application discloses a gate driver on array (GOA) circuit of a display panel. The GOA circuit includes a first GOA unit comprising a unit-circuitry structure having a pull-up node commonly coupled to three output transistors to control outputting of a first set of three gate-driving signals respectively to a first set of three gate lines associated with the display panel. The GOA circuit additionally includes a second GOA unit comprising a substantially same unit-circuitry structure cascaded with the first GOA unit and configured to control outputting a second set of three gate-driving signals respectively to a second set of three gate lines associated with the display panel. Moreover, the GOA circuit includes a capacitor connected from one in the second set of three output terminals of the second GOA unit to the pull-up node of the first GOA unit.

公开(公告)号：US20210201840A1

公开(公告)日：2021-07-01

申请号：US16084027

申请日：2018-04-08

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Guangliang Shang ,  Liugang Zhou ,  Haoliang Zheng ,  Yaoqiu Jing ,  Mingfu Han ,  Seungwoo Han

IPC: G09G3/36

Abstract: The present disclosure is related to a driving circuit of a display panel. The driving circuit may include a turn-on voltage adjusting circuit. The turn-on voltage adjusting circuit may include a control subcircuit and a switching and voltage division subcircuit. The switching and voltage division subcircuit may include a switching subcircuit and a basic voltage division subcircuit. The switching subcircuit may be configured to perform voltage division of a signal outputted by the output terminal of the control subcircuit to form a voltage division feedback signal of the corresponding resolution under control of the control signal and output the voltage division feedback signal to the voltage division feedback node.

公开(公告)号：US20200258463A1

公开(公告)日：2020-08-13

申请号：US15768309

申请日：2017-10-31

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Jiha Kim ,  Seungwoo Han ,  Guangliang Shang ,  Haoliang Zheng ,  Xing Yao ,  Zhichong Wang ,  Mingfu Han ,  Lijun Yuan ,  Yunsik IM ,  Jing Lv ,  Xue Dong

IPC: G09G3/36 ,  G11C19/28

Abstract: A shift register unit cascaded in a gate drive circuit, wherein the shift register unit comprises: a control circuit configured to output a control signal, at least two buffer circuits coupled to the control circuit, each of the at least two buffer circuits configured to output scan signal to a gate line. As such, the scan signals output from the at least two buffer circuits would be synchronized so that the gate lines respectively coupled to the two buffer circuits can be scanned simultaneously.

公开(公告)号：US10504469B2

公开(公告)日：2019-12-10

申请号：US15768948

申请日：2017-10-17

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Jiha Kim ,  Seung Woo Han ,  Guangliang Shang ,  Xing Yao ,  Haoliang Zheng ,  Mingfu Han ,  Zhichong Wang ,  Lijun Yuan ,  Yun Sik Im ,  Jing Lv ,  Yinglong Huang ,  Xue Dong

IPC: G09G3/36 ,  G11C19/28 ,  G09G3/3266 ,  G09G3/20 ,  G11C19/18

Abstract: A shift-buffer circuit, a gate driving circuit, a display panel, a display device, and a driving method. The shift-buffer circuit includes: a shift register and a plurality of buffers connected with the shift register. The shift register includes a shift output terminal; the shift register is configured to output a shift output signal from the shift output terminal, in response to a shift clock signal; each of the buffers includes a buffer input terminal and a buffer output terminal, the buffer input terminal being connected with the shift output terminal; each of the buffers is configured to output a buffer output signal from the buffer output terminal, in response to a buffer clock signal.

公开(公告)号：US10475409B2

公开(公告)日：2019-11-12

申请号：US15796463

申请日：2017-10-27

Applicant: BOE Technology Group Co., Ltd.

Inventor： Mingfu Han ,  Xing Yao ,  Guangliang Shang ,  Haoliang Zheng ,  Seung-Woo Han ,  Jiha Kim ,  Lijun Yuan ,  Zhichong Wang

IPC: G11C19/00 ,  G09G3/36 ,  G06F3/041 ,  G11C19/28

Abstract: The present disclosure discloses a gate drive circuit, a display panel and a driving method for the gate drive circuit. The gate drive circuit includes a plurality of shift register units connected in cascade; and further includes: buffer units which are in a one-to-one correspondence with shift register units at all levels, and touch control switch units which are in a one-to-one correspondence with shift register units at even levels. Each buffer unit in the gate drive circuit can increase the holding time of the effective pulse signal output by the shift register unit at a corresponding level by one line before resetting, and the effective pulse signal output by a buffer unit at an even level under the control of a touch control unit and the effective pulse signal output by a buffer unit at an adjacent previous odd level are reset at the same time.

公开(公告)号：US10276087B2

公开(公告)日：2019-04-30

申请号：US15326370

申请日：2015-12-14

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Guangliang Shang ,  Seung Woo Han ,  Mingfu Han ,  Haoliang Zheng ,  Yanfeng Wang

IPC: G09G3/20

Abstract: The present disclosure discloses a GOA unit driving circuit and a driving method thereof, a display panel and a display device. The disclosure relates to field of display technology, and solves the technical issue of increased power consumption of the display device due to the power consumption of the parasitic capacitance existing in the transistors in the GOA unit. The GOA unit driving circuit comprises a plurality of sets of GOA units, each of which includes at least one GOA unit; a plurality of clock selecting units, which are in one-to-one correspondence with the plurality of sets of GOA units, and each clock selecting unit is connected to a corresponding set of GOA units and connected to one of a plurality of clock signal terminals and at least one of a plurality of clock selection signal terminals, respectively. An intersection of any two sets of GOA units in the plurality of sets of GOA unit is an empty set, and each clock selecting unit transmits a signal of the clock signal terminal to which the clock selecting unit is connected to the corresponding set of GOA units, under control of a signal of the at least one clock selection signal terminal to which the clock selecting unit is connected. The GOA unit driving circuit provided by the present disclosure may be applied to a display device.

公开(公告)号：US10269290B2

公开(公告)日：2019-04-23

申请号：US15680416

申请日：2017-08-18

Applicant: BOE Technology Group Co., Ltd.

Inventor： Guangliang Shang ,  Mingfu Han ,  Haoliang Zheng ,  Han-Seung- Woo ,  Im-Yun- Sik ,  Jing Lv ,  Yinglong Huang ,  Jun-Jung- Mok ,  Xue Dong ,  Zhichong Wang ,  Xing Yao ,  Lijun Yuan ,  Zhihe Jin

IPC: G09G3/36 ,  G09G3/20 ,  G11C19/28 ,  G09G3/3266

Abstract: Embodiments of the present disclosure provide a shift register unit, a driving method thereof, a gate driving circuit, and a display device. The shift register unit comprises an input circuit, a reset circuit, a plurality of output circuits, a plurality of pull-down circuits and a plurality of pull-down control circuits. During a first time period, all of signals output by the plurality of output circuits are valid. During a second time period, at least one of the signals output by the plurality of output circuits is invalid, wherein the second time period comprises a first sub-period and a second sub-period, and the state of at least one of the signals output by the plurality of output circuits during the first sub-period is opposite to the state thereof during the second sub-period. The shift register unit may enable transistors in a pixel circuit to switch between ON and OFF states, so as to extend lifetime of the transistors.

公开(公告)号：US10217411B2

公开(公告)日：2019-02-26

申请号：US14785953

申请日：2014-11-21

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Guangliang Shang

IPC: G09G3/3258 ,  G09G3/3233

Abstract: Disclosed are a display driving circuit and a driving method thereof, and a display apparatus. The display driving circuit comprises a control unit (13), a light emitting device (20) and a collection unit (21). The collection unit (21) is connected with one terminal of the light emitting device (20), the control unit (13) and a collection signal input terminal (Fn) respectively, and is configured to collect brightness of the light emitting device (20) according to a signal input from the collection signal input terminal (Fn) and feed a collection result to the control unit (13); the control unit (13) is connected with the one terminal of the light emitting device (20) and the collection unit (21) respectively, and is configured to adjust an actual light emitting brightness value (L) of the light emitting device (20) to a target brightness value (D) according to the collection result; and the other terminal of the light emitting device (20) is connected with a first voltage (VSS), and is configured to emit light under the control of the control unit (13). The display driving circuit can bring uniformity of brightness in light emitted from respective pixel units.