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    EFFICIENT POST-QUANTUM SECURE SOFTWARE UPDATES TAILORED TO RESOURCE-CONSTRAINED DEVICES
    121.
    发明申请
    EFFICIENT POST-QUANTUM SECURE SOFTWARE UPDATES TAILORED TO RESOURCE-CONSTRAINED DEVICES 有权

    公开(公告)号：US20210119789A1

    公开(公告)日：2021-04-22

    申请号：US17133304

    申请日：2020-12-23

    Applicant: Intel Corporation

    Inventor： Santosh Ghosh ,  Marcio Juliato ,  Manoj Sastry

    IPC: H04L9/08 ,  H04L9/06

    Abstract: A method comprises receiving an image of an update for a software module, a rate parameter, an index parameter, and a public key, generating a 32-byte aligned string, computing a state parameter using the 32-byte aligned string, generating a modified message representative, computing a Merkle Tree root node, and in response to a determination that the Merkle Tree root node matches the public key, forwarding, to a remote device, the image of the update for a software module, the state parameter; and the modified message representative.

    POST QUANTUM PUBLIC KEY SIGNATURE OPERATION FOR RECONFIGURABLE CIRCUIT DEVICES
    124.
    发明申请
    POST QUANTUM PUBLIC KEY SIGNATURE OPERATION FOR RECONFIGURABLE CIRCUIT DEVICES 审中-公开

    公开(公告)号：US20190325166A1

    公开(公告)日：2019-10-24

    申请号：US16456339

    申请日：2019-06-28

    Applicant: Intel Corporation

    Inventor： Vikram Suresh ,  Sanu Mathew ,  Rafael Misoczki ,  Santosh Ghosh ,  Raghavan Kumar ,  Manoj Sastry ,  Andrew H. Reinders

    IPC: G06F21/72 ,  G06F21/76 ,  H04L9/32 ,  H04L9/08

    Abstract: Embodiments are directed to post quantum public key signature operation for reconfigurable circuit devices. An embodiment of an apparatus includes one or more processors; and a reconfigurable circuit device, the reconfigurable circuit device including a dedicated cryptographic hash hardware engine, and a reconfigurable fabric including logic elements (LEs), wherein the one or more processors are to configure the reconfigurable circuit device for public key signature operation, including mapping a state machine for public key generation and verification to the reconfigurable fabric, including mapping one or more cryptographic hash engines to the reconfigurable fabric, and combining the dedicated cryptographic hash hardware engine with the one or more mapped cryptographic hash engines for cryptographic signature generation and verification.

    PARALLEL PROCESSING TECHNIQUES FOR HASH-BASED SIGNATURE ALGORITHMS
    125.
    发明申请
    PARALLEL PROCESSING TECHNIQUES FOR HASH-BASED SIGNATURE ALGORITHMS 审中-公开

    公开(公告)号：US20190319802A1

    公开(公告)日：2019-10-17

    申请号：US16456004

    申请日：2019-06-28

    Applicant: Intel Corporation

    Inventor： RAFAEL MISOCZKI ,  Santosh Ghosh ,  Manoj Sastry ,  David Wheeler

    IPC: H04L9/32 ,  H04L9/06 ,  H04L9/00

    Abstract: In one example an apparatus comprises a computer readable memory to store a public key associated with a signing device, communication logic to receive, from the signing device, a signature chunk which is a component of a signature generated by a hash-based signature algorithm, and at least a first intermediate node value associated with the signature chunk, verification logic to execute a first hash chain beginning with the signature chunk to produce at least a first computed intermediate node value, execute a second hash chain beginning with the at least one intermediate node value associated with the signature chunk to produce a first computed final node value, and use the first computed intermediate node value and the first computed final computed node value to validate the signature generated by the hash-based signature algorithm. Other examples may be described.

    HARDWARE ACCELERATION OF BIKE FOR POST-QUANTUM PUBLIC KEY CRYPTOGRAPHY
    126.
    发明申请
    HARDWARE ACCELERATION OF BIKE FOR POST-QUANTUM PUBLIC KEY CRYPTOGRAPHY 审中-公开

    公开(公告)号：US20190319787A1

    公开(公告)日：2019-10-17

    申请号：US16456096

    申请日：2019-06-28

    Applicant: Intel Corporation

    Inventor： ANDREW H. REINDERS ,  Santosh Ghosh ,  Manoj Sastry ,  Rafael Misoczki

    IPC: H04L9/08 ,  G06F7/53 ,  G06F7/72

    Abstract: In one example an apparatus comprises an unsatisfied parity check (UPC) memory, an unsatisfied parity check (UPC) compute block communicatively coupled to the UPC memory, a first error memory communicatively coupled to the UPC compute block, a polynomial multiplication syndrome memory, a polynomial multiplication compute block communicatively coupled to the polynomial multiplication syndrome memory, a second error memory communicatively coupled to the polynomial multiplication compute block, a codeword memory communicatively coupled to the UPC compute block and the polynomial multiplication compute block, a multiplexer communicatively coupled to first error memory and to the polynomial multiplication compute block, and a controller communicatively coupled to the UPC memory, the polynomial multiplication syndrome memory, the codeword memory, and the multiplexer. Other examples may be described.

    TIME RECOVERY FROM ATTACKS ON DELAYED AUTHENTICATION
    129.
    发明申请
    TIME RECOVERY FROM ATTACKS ON DELAYED AUTHENTICATION 有权

    公开(公告)号：US20250106207A1

    公开(公告)日：2025-03-27

    申请号：US18373160

    申请日：2023-09-26

    Applicant: Intel Corporation

    Inventor： Marcio Juliato ,  Manoj Sastry ,  Christopher Gutierrez ,  Vuk Lesi ,  Shabbir Ahmed

    IPC: H04L9/40

    Abstract: Techniques to perform time recovery from attacks on delayed authentication in a time synchronized network are described. One embodiment comprises a method for decoding time information and a message authentication code (MAC) from a time message, the time information to synchronize a local clock for a device to a network time of a time synchronized network (TSN), and the MAC to authenticate the time message, determining whether the time message is authentic using the MAC, discarding the time information when the time message is not authentic, performing a bounded search to identify authentic time information using the MAC, and passing the authentic time information to a clock manager to synchronize the local clock to the network time of the TSN when the authentic time information is identified. Other embodiments are described and claimed.

    CONTINUED TIME SYNCHRONIZATION IN THE PRESENCE OF ATTACKS USING ATTACK-AWARE TWIN
    130.
    发明申请
    CONTINUED TIME SYNCHRONIZATION IN THE PRESENCE OF ATTACKS USING ATTACK-AWARE TWIN 有权

    公开(公告)号：US20250080549A1

    公开(公告)日：2025-03-06

    申请号：US18240822

    申请日：2023-08-31

    Applicant: Intel Corporation

    Inventor： Manoj Sastry ,  Christopher Gutierrez ,  Marcio Rogerio Juliato ,  Shabbir Ahmed ,  Vuk Lesi

    IPC: H04L9/40 ,  G06F1/04

    Abstract: Techniques for an attack-aware digital twin in a time sensitive network are described. A method includes receiving time information for a network by an attack-aware digital twin (AADT), the AADT to simulate operations of a clock manager for a node in the network based on models of the clock manager, generating model clock control information to adjust a clock to a network time for the network, the model clock control information to contain a malicious time sample introduced by a time desynchronization attack in the network, and removing the malicious time sample from the model clock control information to adjust the clock to the network time for the network. Other embodiments are described and claimed.

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