公开(公告)号：US07200069B2

公开(公告)日：2007-04-03

申请号：US10273512

申请日：2002-10-18

申请人： Seong-Jin Jang ,  Jin-Seok Kwak

发明人： Seong-Jin Jang ,  Jin-Seok Kwak

IPC分类号： G06F12/00

CPC分类号： G11C7/1087 ,  G06F13/1689 ,  G11C7/1078 ,  G11C2207/107

摘要： A semiconductor memory system, a memory control circuit and a semiconductor memory device are disclosed. The system includes a memory control circuit for generating a data strobe signal and a data load signal in synchronization with each other. The memory circuit, which can be an SDRAM memory circuit, receives the data strobe signal and the data load signal and writes data in response to the two synchronous signals. Because the signal are synchronous, parameters introduced by timing variations caused by different signal domains are eliminated. As a result, high-frequency operation of the system is greatly improved.

摘要翻译： 公开了半导体存储器系统，存储器控制电路和半导体存储器件。 该系统包括用于彼此同步地产生数据选通信号和数据负载信号的存储器控​​制电路。 可以是SDRAM存储器电路的存储电路接收数据选通信号和数据负载信号，并响应于两个同步信号写入数据。 由于信号是同步的，消除了由不同信号域引起的定时变化引入的参数。 结果，系统的高频操作大大提高。

公开(公告)号：US20060268624A1

公开(公告)日：2006-11-30

申请号：US11419155

申请日：2006-05-18

申请人： Seong-Jin Jang

发明人： Seong-Jin Jang

IPC分类号： G11C7/10

CPC分类号： G11C29/14 ,  G11C29/12015 ,  G11C29/32

摘要： A semiconductor memory device includes a serial to parallel converter configured to generate parallel data at a parallel data rate in response to first serial data at first serial data rate in a first mode and configured to generate the parallel data at the parallel data rate in response to a second serial data at second serial data rate in a second mode, wherein the second serial data rate is less than the first serial data rate, and a data write circuit configured to provide the parallel data to a memory cell array.

摘要翻译： 半导体存储器件包括串行到并行转换器，其被配置为响应于处于第一模式的第一串行数据速率的第一串行数据以并行数据速率产生并行数据，并且被配置为响应于并行数据速率以并行数据速率生成并行数据 以第二模式的第二串行数据速率的第二串行数据，其中所述第二串行数据速率小于所述第一串行数据速率，以及数据写入电路，被配置为将并行数据提供给存储器单元阵列。

公开(公告)号：US20060250861A1

公开(公告)日：2006-11-09

申请号：US11416077

申请日：2006-05-03

申请人： Kwang-II Park ,  Young-Hyun Jun ,  Seong-Jin Jang ,  Ho-Young Song

发明人： Kwang-II Park ,  Young-Hyun Jun ,  Seong-Jin Jang ,  Ho-Young Song

IPC分类号： G11C7/00

CPC分类号： G11C7/1051 ,  G11C7/1066 ,  G11C7/1072

摘要： A latency signal generating method and a corresponding semiconductor memory device, among other things, are disclosed. Such a method includes: receiving a clock signal for the semiconductor memory device; receiving a mode characterization signal; providing the DQS; and adapting the duration of a preamble state of the DQS according to the mode characterization signal to promote conformance of a strobe state of the DQS with the clock signal.

摘要翻译： 公开了等待信号产生方法和相应的半导体存储器件。 这种方法包括：接收半导体存储器件的时钟信号; 接收模式表征信号; 提供DQS; 以及根据模式表征信号调整DQS的前导码状态的持续时间，以促进DQS的选通状态与时钟信号的一致性。

公开(公告)号：US20060083081A1

公开(公告)日：2006-04-20

申请号：US11251787

申请日：2005-10-18

申请人： Kwang-Il Park ,  Seong-Jin Jang ,  Ho-Young Song

发明人： Kwang-Il Park ,  Seong-Jin Jang ,  Ho-Young Song

IPC分类号： G11C7/00

CPC分类号： G11C7/1051 ,  G11C7/1066 ,  G11C2207/2254

摘要： An output data strobe signal generating method and a memory system that includes a plurality of semiconductor memory devices, and a memory controller for controlling the semiconductor memory devices, wherein the memory controller provides a command signal and a chip selecting signal to the semiconductor memory devices. One or more of the semiconductor memory devices may detect a read command and a dummy read command in response to the command signal and the chip selecting signal and generate one or more preamble signals based on a calculated preamble cycle number.

摘要翻译： 输出数据选通信号产生方法和包括多个半导体存储器件的存储器系统以及用于控制半导体存储器件的存储器控​​制器，其中存储器控制器向半导体存储器件提供命令信号和片选信号。 一个或多个半导体存储器件可以响应于命令信号和芯片选择信号来检测读取命令和伪读取命令，并且基于所计算的前导码周期数生成一个或多个前导信号。

公开(公告)号：US06762620B2

公开(公告)日：2004-07-13

申请号：US10235694

申请日：2002-09-05

申请人： Seong-Jin Jang ,  Jin-Seok Kwak

发明人： Seong-Jin Jang ,  Jin-Seok Kwak

IPC分类号： H03K1716

CPC分类号： H04L25/0298 ,  H03K19/0005

摘要： A system and method allows for multiple modes of termination, including termination by a fixed value that is preprogrammed, and by a variable value that can, for example, be measured and determined by a self-calibration circuit. Multiple termination values can be achieved within a single device. This configuration is especially applicable to devices that have different loadings for address and data signals, for example in a configuration having a common, shared address bus, and multiple, localized data buses.

摘要翻译： 系统和方法允许多种终止模式，包括通过预编程的固定值的终止，以及可以例如由自校准电路测量和确定的可变值。 可以在单个设备内实现多个终止值。 该配置特别适用于具有地址和数据信号的不同负载的设备，例如在具有公共共享地址总线和多个本地化数据总线的配置中。

公开(公告)号：US06693482B2

公开(公告)日：2004-02-17

申请号：US10210605

申请日：2002-08-01

申请人： Seong-Jin Jang

发明人： Seong-Jin Jang

IPC分类号： G05F110

CPC分类号： H02M3/073

摘要： A voltage generation circuit generates an output voltage at an output node thereof by sharing charge between a first node and a second node so as to increase a potential at the second node from a first voltage to a second voltage. The first node is charged to a third voltage and the second node is driven to a fourth voltage that is greater than the third voltage. Charge is shared between the first node and the second node so that the first and second nodes reach a common fifth voltage, which is between the third and fourth voltages. The first node is driven to a sixth voltage, which is greater than the fourth voltage. Charge is shared between the first node and the output node to generate the output voltage thereat.

摘要翻译： 电压产生电路通过在第一节点和第二节点之间共享电荷来在其输出节点处产生输出电压，以便将第二节点处的电位从第一电压增加到第二电压。 第一节点被充电到第三电压，并且第二节点被驱动到大于第三电压的第四电压。 电荷在第一节点和第二节点之间共享，使得第一和第二节点达到第三和第四电压之间的公共第五电压。 第一节点被驱动到大于第四电压的第六电压。 电荷在第一节点和输出节点之间共享，以在其上产生输出电压。

公开(公告)号：US06667895B2

公开(公告)日：2003-12-23

申请号：US10192901

申请日：2002-07-10

申请人： Seong-Jin Jang ,  Young-Hyun Jun ,  Chang-Man Khang

发明人： Seong-Jin Jang ,  Young-Hyun Jun ,  Chang-Man Khang

IPC分类号： G11C506

CPC分类号： G11C5/063 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit comprises a substrate having circuitry integrated with the substrate. Switching circuitry is selectably operable to configure signal paths to alternative mirrored pads over the substrate. At least one of the first and second signal paths may comprise a buffer in series between the switching circuit and its respective pad.

公开(公告)号：US5926043A

公开(公告)日：1999-07-20

申请号：US892841

申请日：1997-07-11

申请人： Seong-Jin Jang

发明人： Seong-Jin Jang

IPC分类号： G11C11/417 ,  G11C7/00 ,  G11C11/401 ,  G11C11/409 ,  H03K19/0185 ,  H03K5/153

CPC分类号： H03K19/018585

摘要： An output circuit for a semiconductor device that outputs an output voltage based on a received external signal. The output circuit has an interface that receives the external signal, and a comparing unit that compares the external signal with a plurality of predetermined threshold voltages. The comparing unit outputs a voltage driving signal based on the comparison results. Also, the output circuit has an output unit that outputs the output voltage based on the voltage driving signal from the comparing unit.

摘要翻译： 一种用于基于接收的外部信号输出输出电压的半导体器件的输出电路。 输出电路具有接收外部信号的接口，以及将外部信号与多个预定阈值电压进行比较的比较单元。 比较单元根据比较结果输出电压驱动信号。 此外，输出电路具有输出单元，该输出单元基于来自比较单元的电压驱动信号输出输出电压。