公开(公告)号：US11003448B2

公开(公告)日：2021-05-11

申请号：US16116869

申请日：2018-08-29

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Gregory Edvenson ,  David Hulton ,  Jeremy Chritz

IPC: G06F15/76 ,  G06F15/80 ,  G06F9/30 ,  G06N20/00 ,  G06F15/78 ,  G06F9/38

Abstract: Apparatuses and methods are disclosed for an FPGA architecture that may improve processing speed and efficiency in processing less complex operands. Some applications may utilize operands that are less complex, such as operands that are 1, 2, or 4 bits, for example. In some examples, the DSP architecture may skip or avoid processing all received operands or may process a common operand more frequently than other operands. An example apparatus may include configurable logic blocks including DSP slices and an interconnected coupling the configurable logic blocks. An operand register of a DSP slice may include an operand input that is coupled to an output of that DSP slice.

公开(公告)号：US20210098047A1

公开(公告)日：2021-04-01

申请号：US17121466

申请日：2020-12-14

Applicant: Micron Technology, Inc.

Inventor： Jonathan D. Harms ,  David Hulton ,  Jeremy Chritz

IPC: G11C11/406 ,  G06F11/10 ,  G11C29/02 ,  G11C29/52

Abstract: Methods and apparatus for dynamically adjusting performance of partitioned memory. In one embodiment, the method includes receiving one or more configuration requests for the memory device, determining whether to grant the one or more configuration requests for the memory device, in response to the determining, implementing the one or more configuration requests within the memory device and operating the memory device in accordance with the implementing. The adjusting of the performance for the partitioned memory includes one or more of enabling/disabling refresh operations, altering a refresh rate for the partitioned memory, enabling/disabling error correcting code (ECC) circuity for the partitioned memory, and/or altering a memory cell architecture for the partitioned memory. Systems and applications that may benefit from the dynamic adjustment of performance are also disclosed.

公开(公告)号：US20210089637A1

公开(公告)日：2021-03-25

申请号：US17024462

申请日：2020-09-17

Applicant: Micron Technology, Inc.

Inventor： Jaime Cummins ,  Jeremy Chritz ,  Tamara Schmitz ,  Robert F. Gazdzinski

IPC: G06F21/32 ,  H04L29/08 ,  H04L29/06

Abstract: Methods and apparatus for biometric data maintenance, access and distribution across two or more experiential and/or network domains. In one embodiment, a 5G NR-based network architecture is provided which allows ultra-low latency and effectively user-imperceptible biometric data use for e.g., authentication and maintenance of user state across multiple domains via multiple constituent user devices (e.g., UEs). The network architecture includes both (i) a distributed biometric database (BDB) model wherein relevant biometric data for individuals/UEs is intelligently cached in various portions of the distributed database, and (ii) centralized and local BAEs (biometric analytics entities) which manage the aforementioned intelligent caching, as well as network configuration using one or both of 5G NR network “slicing” and CU/DU split options to optimize end-user biometric-related applications such as those providing identification/authentication, AR functions, VR functions or yet others.

公开(公告)号：US10956315B2

公开(公告)日：2021-03-23

申请号：US16043921

申请日：2018-07-24

Applicant: Micron Technology, Inc.

Inventor： Fa-Long Luo ,  Jaime Cummins ,  Tamara Schmitz ,  Jeremy Chritz

IPC: G06F12/02 ,  G06F12/0893 ,  G06F12/0864 ,  G06F12/06

Abstract: Methods, apparatuses, and systems for tensor memory access are described. Multiple data located in different physical addresses of memory may be concurrently read or written by, for example, employing various processing patterns of tensor or matrix related computations. A memory controller, which may comprise a data address generator, may be configured to generate a sequence of memory addresses for a memory access operation based on a starting address and a dimension of a tensor or matrix. At least one dimension of a tensor or matrix may correspond to a row, a column, a diagonal, a determinant, or an Nth dimension of the tensor or matrix. The memory controller may also comprise a buffer configured to read and write the data generated from or according to a sequence of memory of addresses.

公开(公告)号：US10886998B2

公开(公告)日：2021-01-05

申请号：US16282916

申请日：2019-02-22

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Fa-Long Luo ,  Jaime Cummins ,  Tamara Schmitz ,  Jeremy Chritz

IPC: H04W4/00 ,  H04B7/08 ,  H04L27/26 ,  H04B1/04

Abstract: Examples described herein include systems and methods which include wireless devices and systems with examples of mixing input data with coefficient data specific to a processing mode selection. For example, a computing system with processing units may mix the input data for a transmission in a radio frequency (RF) wireless domain with the coefficient data to generate output data that is representative of the transmission being processed according to a specific processing mode selection. The input data is mixed with coefficient data at layers of multiplication/accumulation processing units (MAC units). The processing mode selection may be associated with an aspect of a wireless protocol. Examples of systems and methods described herein may facilitate the processing of data for 5G wireless communications in a power-efficient and time-efficient manner.

公开(公告)号：US10805128B2

公开(公告)日：2020-10-13

申请号：US16105915

申请日：2018-08-20

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Fa-Long Luo ,  Jeremy Chritz ,  Jaime Cummins ,  Tamara Schmitz

IPC: H04L25/08 ,  H04L5/14 ,  H04L5/00 ,  H04B1/12 ,  H04B1/10 ,  H04B1/525 ,  H04B17/21 ,  H04L25/02 ,  H04L25/03 ,  H04L27/26 ,  H04B17/345 ,  H04B7/04

Abstract: Examples described herein include systems and methods which include wireless devices and systems with examples of full duplex compensation with a self-interference noise calculator. The self-interference noise calculator may be coupled to antennas of a wireless device and configured to generate adjusted signals that compensate self-interference. The self-interference noise calculator may include a network of processing elements configured to combine transmission signals into sets of intermediate results. Each set of intermediate results may be summed in the self-interference noise calculator to generate a corresponding adjusted signal. The adjusted signal is received by a corresponding wireless receiver to compensate for the self-interference noise generated by a wireless transmitter transmitting on the same frequency band as the wireless receiver is receiving.

公开(公告)号：US20200305161A1

公开(公告)日：2020-09-24

申请号：US16893740

申请日：2020-06-05

Applicant: Micron Technology, Inc.

Inventor： Fa-Long Luo ,  Jaime Cummins ,  Tamara Schmitz ,  Jeremy Chritz

IPC: H04W72/04 ,  H04W72/08 ,  H04B10/2575

Abstract: Examples described herein include systems and methods which include wireless devices and systems with examples of configuration modes for baseband units (BBU) and remote radio heads (RRH). For example, a computing system including a BBU and a RRH may receive a configuration mode selection including information indicative of a configuration mode for respective processing units of the BBU and the RRH. The computing system may allocate the respective processing units to perform wireless processing stages associated with a wireless protocol. The BBU and/or the RRH may generate an output data stream based on the mixing of coefficient data with input data at the BBU and/or the RRH. Examples of systems and methods described herein may facilitate the processing of data for 5G (e.g., New Radio (NR)) wireless communications in a power-efficient and time-efficient manner.

公开(公告)号：US20200285486A1

公开(公告)日：2020-09-10

申请号：US16292091

申请日：2019-03-04

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Jeremy Chritz ,  Tamara Schmitz ,  Fa-Long Luo ,  DAVID Hulton

IPC: G06F9/448 ,  G06F9/38 ,  G06F15/82 ,  G06F12/0842

Abstract: Methods, apparatuses, and systems for implementing data flows in a processor are described herein. A data flow manager may be configured to generate a configuration packet for a compute operation based on status information regarding multiple processing elements of the processor. Accordingly, multiple processing elements of a processor may concurrently process data flows based on the configuration packet. For example, the multiple processing elements may implement a mapping of processing elements to memory, while also implementing identified paths, through the processor, for the data flows. After executing the compute operation at certain processing elements of the processor, the processing results may be provided. In speech signal processing operations, the processing results may be compared to phonemes to identify such components of human speech in the processing results. Once dynamically identified, the processing elements may continue comparing additional components of human speech to facilitate processing of an audio recording, for example.

公开(公告)号：US10601471B1

公开(公告)日：2020-03-24

申请号：US16115866

申请日：2018-08-29

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Fa-Long Luo ,  Jaime Cummins ,  Tamara Schmitz ,  Jeremy Chritz

IPC: H04B7/02 ,  H04B7/0413 ,  G06N3/08 ,  G06N3/04

Abstract: Examples described herein include systems and methods, including wireless devices and systems with neuron calculators that may perform one or more functionalities of a wireless transceiver. The neuron calculator calculates output signals that may be implemented, for example, using accumulation units that sum the multiplicative processing results of ordered sets from ordered neurons with connection weights for each connection between an ordered neuron and outputs of the neuron calculator. The ordered sets may be a combination of some input signals, with the number of signals determined by an order of the neuron. Accordingly, a kth-order neuron may include an ordered set comprising product values of k input signals, where the input signals are selected from a set of k-combinations with repetition. As an example in a wireless transceiver, the neuron calculator may perform channel estimation as a channel estimation processing component of the receiver portion of a wireless transceiver.

公开(公告)号：US10554375B2

公开(公告)日：2020-02-04

申请号：US15701007

申请日：2017-09-11

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Fa-Long Luo ,  Tamara Schmitz ,  Jeremy Chritz ,  Jaime Cummins

IPC: H04L5/14 ,  H04B1/525 ,  H04B7/06 ,  H04W4/70 ,  H04B7/026 ,  H04B7/08 ,  H04W4/40 ,  H04W76/14 ,  H04L5/00 ,  H04L25/02

Abstract: Examples described herein include apparatuses and methods for full duplex device-to-device cooperative communication. Example systems described herein may include self-interference noise calculators. The output of a self-interference noise calculator may be used to compensate for the interference experienced due to signals transmitted by another antenna of the same wireless device or system. In implementing such a self-interference noise calculator, a selected wireless relaying device or wireless destination device may operate in a full-duplex mode, such that relayed messages may be transmitted as well as information from other sources or destinations during a common time period (e.g., symbol, slot, subframe, etc.).